Abstract
A drain current local variability compact model due to random fluctuation of channel length induced by line edge roughness/line width roughness (LER/LWR) is derived here. The random fluctuation of channel length leads to correlated fluctuations of threshold voltage and effective mobility of the current carriers. Therefore, an unified compact model is required to combine all the causes. Our model is based on the principle of propagation of variance. For the model verification purpose, calibrated technology computer aided design (TCAD) simulation platform is extensively used for all possible bias regions and several LER profile parameters. Channel profile optimization is critically studied with respect to different LER parameters, aiming reduction of ID variability. The model is further extended for SOI (Silicon-on-insulator) transistor and validated with literature data of threshold voltage and on-current variability.
Highlights
In nano-scale CMOS analog circuits, mismatch between the drain currents of two identical transistors placed adjacent to each other is attributed to few Sarmista Sengupta, Soumya Pandit major causes like random discrete dopant effect (RDD), line edge/line width roughness (LER/LWR), metal gate granularity etc [1]
By re-definitions of few device parameters, the model may be extended to other device structures such as SOI structures, which we have shown in this work. (ii) The present model of local drain current variability being a compact model gives an insight on the minimization approaches of variability through device design and optimization. (iii) The model does not involve purely empirical parameters
The channel length variation leads to correlated variation of threshold voltage and effective mobility of the charge carriers
Summary
The line edge roughness (LER) phenomenon arises due to i) sub-wavelength lithography and/or ii) intrinsic non-uniformity of the photoresist used in the process technology [2]. LER leads to variation in critical dimension of the feature size. The amplitude of roughness (σLER) remains almost same and does not scale down with technology. As the device dimensions, especially the channel length and width becomes comparable with this magnitude, LER/LWR-induced performance variability of a device/circuit appears to be quite critical [3]
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