Silicon-on-insulator Devices Research Articles

A Novel High Voltage Ultra-Thin SOI-LDMOS With Sectional Linearly Doped Drift Region

A novel high voltage ultra-thin silicon on insulator (SOI) lateral double diffused metal oxide semiconductor field effect transistor (LDMOS) with a sectional linearly doped drift region is proposed and experimentally realized in this letter. The new device features a sectional linear doping (SLD) in a 0.17 μm SOI layer with a source field plate covering the full drift region. Low specific on-resistance Ron,sp is obtained by increasing the local doping concentration of the high resistance region. An analytical model is developed to provide the design guidance for the thin SOI devices with the field plate. The experimental results of the SOI SLD-LDMOS demonstrate that the new device shows a high breakdown voltage V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</sub> of 960 V with a superior figure of merit (FOM = V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</sub> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> / R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> ) of 5.98 MW/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> when comparing with other reported thin SOI devices. Good agreements are observed between the model and the experimental results.

Comparison of Total-Ionizing-Dose Effects in Bulk and SOI FinFETs at 90 and 295 K

Bulk and silicon-on-insulator (SOI) n-channel FinFETs with fin widths of 15-40 nm and channel lengths of 45 and 1000 nm were irradiated with 1.8 MeV protons at temperatures of 295 and 90 K. Bulk and SOI FinFETs show improved transconductance and steeper subthreshold slopes before irradiation at 90 K than at 295 K. Increased off-state leakage currents are observed for longer channel bulk FinFETs for doses above 300-500 krad (SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) for 295 and 90 K irradiation, and at lower doses for shorter channel devices. Threshold-voltage shifts for irradiation up to 1 Mrad(SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) are greater for SOI devices at 90 K than at 295 K due to enhanced charge trapping in the buried oxide (BOX). TCAD simulations provide insight into radiation-induced trapped-charge densities in the SOI devices.

Temperature dependence of single-event transient response in devices with selective-buried-oxide structure

The silicon-on-insulator (SOI) device has been found to possess low leakage current and high operation speed due to reduced internal capacitances. The sensitive volume for charge collection in SOI device is smaller than that in bulk-silicon device, which improves the ability of SOI devices to resist single-event effect (SEE). In spite of these benefits, the SOI device has certain undesirable effects such as the kink effect. To mitigate the kink effect, selective-buried-oxide (SELBOX) SOI structure has been introduced. Space-borne electronic circuits based on SOI technology recently have been used in high radiation and extreme temperature environments. However, temperature affects internal carrier transport process and impact ionization process, which makes single-event transient (SET) pulse widths increased. Most of previous researches regarding temperature dependence of SEE were for SOI floating-body devices. But the influence of operating temperature on SEE of SELBOX SOI devices are yet unclear. In this paper, an SOI floating-body device and a SELBOX SOI device under 90 nm process are established by three-dimensional device simulation, and then temperature dependence of SET response in partially depleted SOI inverter chains is studied by a mixed-mode approach over a temperature range from 200 K to 450 K. Simulation results show that the N-type SELBOX SOI device has a better ability to resist SEE than the floating-body device, while the P-type SELBOX SOI device has the same ability to resist SEE at high linear energy transfer value as the floating-body device. And temperature dependence analysis of charge collection indicates that there is only drift-diffusion process in the N-type SELBOX SOI device. The amount of charge collection in the N-type SELBOX SOI device almost does not change with the increase of temperature. In addition, both the P-type SELBOX SOI device and the P-type floating-body device have a bipolar amplification process. With the increase of temperature, the bipolar amplification process in the substrate turns more serious. However, it suppresses the bipolar amplification process of the source because of SELBOX structure, so that the amount of charge collection is reduced in the drain significantly. According to our simulation results, compared with the floating-body device, the SELBOX SOI device can very well suppress the influence of temperature on SET pulse.

Transient Response of 0.18-&lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;${\mu}$ &lt;/tex-math&gt; &lt;/inline-formula&gt;m SOI MOSFETs and SRAM Bit-Cells to Heavy-Ion Irradiation for Variable SOI Film Thickness

In this paper, the effect of silicon-on-insulator (SOI) thickness scaling in fully and partially depleted SOI (FD-SOI and PD-SOI) devices is analyzed for their transient response to heavy-ion irradiation. We have analyzed radiation performance of FD-/PD-SOI MOSFETs and 6-T SRAM bit-cells, conforming to 0.18- $\mu \text{m}$ technology node, using calibrated 2-D TCAD simulations. We, for the first time, report here that while SRAMs designed with FD-SOI devices have superior hardness to heavy-ion radiation, they are also more sensitive to SOI film thickness than the SRAMs designed with PD-SOI devices. The slopes of the critical linear energy transfer (LETC) to SOI film thickness curves are +1000 and −950 000 $\text {MeV}\cdot \text {cm/mg}$ for PD-SOI and FD-SOI devices at 1.8V supply voltage ( ${V} _{\text {DD}}$ ), respectively. The negative slope for FD-SOI device indicates better radiation performance for thinner silicon films, while a positive slope in PD-SOI device indicates better radiation performance with thicker silicon films. We further investigated the effect of ambient temperature and supply voltage ( ${V} _{\text {DD}}$ ) on SOI thickness scaled FD-/PD-SOI devices. We show that increasing ${V} _{\text {DD}}$ results in increased generated charge due to the heavy-ion at transistor level, whereas LETC of the SRAM bit-cell improves with increasing ${V} _{\text {DD}}$ . We further highlight that the heavy-ion radiation response as a function of ambient temperature depends not only on the thickness of the SOI film but also on the LET of the impinging heavy-ion.

Optimisation of the design of SOI microdosimeters for hadron therapy quality assurance

Silicon-on-insulator (SOI) microdosimeters offer a promising method for routine quality assurance (QA) for hadron therapy due to their ease of operation and high spatial resolution. However, one complication which has been shown previously is that the traditional use of the mean chord length, , calculated using Cauchy’s formula, for SOI devices in clinical carbon ion fields is not appropriate due to the strong directionality of the radiation field. In a previous study, we demonstrated that the mean path length, , which is the mean path of charged particles in the sensitive volume (SV), is a more appropriate method to obtain microdosimetric quantities and biological relevant values, namely the relative biological effectiveness (RBE) by means of the microdosimetric kinetic model. The previous work, which was limited to mono-energetic ion beams typical of heavy ion therapy (HIT), is extended here to investigate the in a pristine proton beam as well as for spread out Bragg peaks (SOBP) for both proton and carbon ion clinical beams. In addition, the angular dependence of the SOI device for a number of different SV designs is also investigated to quantify the effects which the alignment has on the . It is demonstrated that the can be accurately estimated along the depth of a pristine or SOBP using the energy deposition spectra for both proton and ion beams. This observation allows a quick and accurate estimation of the for experimental use.

Negative bias temperature instability in SOI‐like p‐type metal oxide semiconductor devices

A silicon on insulator (SOI)-like bulk silicon (SLBS) MOSFET has been recently reported. An ‘n/p-/n+’ structure was contained in SLBS P Metal Oxide Semiconductor (PMOS) device, with ‘p-’ is made of 4H-SiC. This p-layer is fully depleted. In this work, negative bias temperature instability (NBTI) of SLBS pMOSFET is studied and compared with that in bulk and Fully Depleted (FD) SOI PMOSFET. The effects of stress temperature and body bias on NBTI of SLBS device are also be studied in this work. The work demonstrates an advantage of SLBS over bulk and FD SOI devices.

Static power characteristics of selective buried oxide CMOS devices

AbstractSelective buried oxide (SELBOX) Metal‐Oxide‐Semiconductor Field‐Effect Transistor (MOSFET) structure can be used to reduce the kink effect and self‐heating problems associated with the silicon on insulator (SOI) MOSFET devices while maintaining the advantages of bulk MOSFET. In this paper, static power dissipation of SELBOX structure is investigated and compared with SOI and bulk structures. Various MOSFET structures are simulated and evaluated in terms of their static power dissipation. Only results from 90‐nm Complementary Metal Oxide Semiconductor (CMOS) technology devices are included in this paper. Simulation results using the Silvaco TCAD show that static power dissipation in SELBOX CMOS is similar to that of SOI devices but lower than that of bulk CMOS. Hence, SELBOX structure is found to produce relatively low‐static power dissipation while maintaining high operating speed and reducing self‐heating and kink effect. A mathematical model to describe the static power dissipation in the subthreshold region is also included. Statistical analysis show that the model and fabrication simulation results agree with P &lt; .05 and correlation coefficient of 0.95.

Tensile Strength of Silicon Nanowires Batch-Fabricated into Electrostatic MEMS Testing Device

The tensile strength of a silicon nanowire (SiNW) that had been integrated into a silicon-on-insulator (SOI)-based microelectromechanical system (MEMS) device was measured using electrostatic actuation and sensing. SiNWs of about 150 nm diameter and 5 μm length were batch-fabricated into a 5-μm-thick SOI device layer. Since there was no interface between the SiNW and the MEMS device and the alignment was perfect, the SiNW integration into an SOI-MEMS was expected to be useful for developing highly sensitive biochemical sensors or highly reliable torsional mirror devices. The SiNW was tensile tested using the electrostatic MEMS testing device. The integration was achieved using a combination of anisotropic and an isotropic dry etching of silicon, with an inductively coupled plasma reactive ion etching. A fabricated silicon beam of 800 nm square was thinned by a sacrificial oxidation process. The tensile strength of the wire was 2.6–4.1 GPa, which was comparable to that of microscale silicon MEMS structures. The reliability of such a thin device was successfully verified for future applications of the device structures.

Mechanisms of atmospheric neutron-induced single event upsets in nanometric SOI and bulk SRAM devices based on experiment-verified simulation tool**Project supported by the National Natural Science Foundation of China (Grant No. 11505033), the Science and Technology Research Project of Guangdong Province, China (Grant Nos. 2015B090901048 and 2017B090901068), and the Science and Technology Plan Project of Guangzhou, China (Grant No. 201707010186).

In this paper, a simulation tool named the neutron-induced single event effect predictive platform (NSEEP2) is proposed to reveal the mechanism of atmospheric neutron-induced single event effect (SEE) in an electronic device, based on heavy-ion data and Monte-Carlo neutron transport simulation. The detailed metallization architecture and sensitive volume topology of a nanometric static random access memory (SRAM) device can be considered to calculate the real-time soft error rate (RTSER) in the applied environment accurately. The validity of this tool is verified by real-time experimental results. In addition, based on the NSEEP2, RTSERs of 90 nm–32 nm silicon on insulator (SOI) and bulk SRAM device under various ambient conditions are predicted and analyzed to evaluate the neutron SEE sensitivity and reveal the underlying mechanism. It is found that as the feature size shrinks, the change trends of neutron SEE sensitivity of bulk and SOI technologies are opposite, which can be attributed to the different MBU performances. The RTSER of bulk technology is always 2.8–64 times higher than that of SOI technology, depending on the technology node, solar activity, and flight height.

Metastable Electron Traps in Modified Silicon-on-Insulator Wafer**Supported by the National Natural Science Foundation of China under Grant No 61504047, and the Fujian Provincial Department of Science and Technology under Grant No 2016J05159.

We perform the total ionizing radiation and electrical stress experiments to investigate the electrical characteristics of the modified silicon-on-insulator (SOI) wafers under different Si ion implantation conditions. It is confirmed that Si implantation into the buried oxide can create deep electron traps with large capture cross section to effectively improve the antiradiation capability of the SOI device. It is first proposed that the metastable electron traps accompanied with Si implantation can be avoided by adjusting the peak location of the Si implantation reasonably.

(Invited) Current Status and Trends in RF Silicon-on-Insulator Material and Device

Radio Frequency (RF) Silicon-on-Insulator (SOI) is today a mainstream technology for several front-end module integrated circuits. The high quality of the trap-rich SOI substrate in terms of low insertion loss and high linearity is at the origin of its commercial success. Partially depleted SOI transistors characterized with a channel length from 180 nm down to 45 nm are currently manufactured on top of the trap-rich substrate. However, there is a growing interest for moving from partially to fully depleted SOI transistors in order to improve the RF and millimeter-waves performance of the transistor at low power consumption. On-going research explores the possibility of combining the best of the digital FD SOI devices and high quality RF SOI substrate to design low power mixed-mode communication system-on-chip.

Research on the radiation hardened SOI devices with single-step Si ion implantation

Silicon-on-insulator (SOI) devices are sensitive to the total ionizing dose effect due to the existence of buried oxide. In this paper, an extra single-step Si ion implantation into buried oxide layer prior to the normal complementary metal–oxide–semiconductor transistor (CMOS) process is used to harden the SOI wafer. The top-Si quality of the hardened SOI wafer is confirmed to be good enough for device manufacturing through various characterization methods. The radiation experiments show that the total ionizing dose tolerance of the Si implanted SOI device is improved significantly. The metastable electron traps introduced by Si implantation is also investigated by electrical stress. The results show that these traps are very instable, and electrons will tunnel into or out of the metastable electron traps quickly after hot-electron-injection or hot-hole-injection.

Improved Single-Event Transient Hardness in Tunnel-Diode Body-Contact SOI nMOS

Single-event transient (SET) responses are compared for floating-body contact, T-gate body-contact (TB), and tunnel-diode body-contact (TDBC) silicon-on-insulator (SOI) MOSFETs. The influence of three body-contact schemes on SET sensitivity is examined via irradiations as functions of position, bias voltage, and device size. The mechanisms of SET in SOI devices are discussed. Although both TB and TDBC schemes suppress floating body effects (FBEs), the TDBC scheme has superior SET hardness because it effectively eliminates charge enhancement due to bipolar amplification originating from FBEs. Thus, TDBC-structure SOI devices can lead to improved single-event upset hardness in static random access memory cells.

Comparative Study of RESURF Si/SiC LDMOSFETs for High-Temperature Applications Using TCAD Modeling

This paper analyses the effect of employing an Si on semi-insulating SiC (Si/SiC) device architecture for the implementation of 600-V LDMOSFETs using junction isolation and dielectric isolation reduced surface electric field technologies for high-temperature operations up to 300 °C. Simulations are carried out for two Si/SiC transistors designed with either PN or silicon-on-insulator (SOI) and their equivalent structures employing bulk-Si or SOI substrates. Through comparisons, it is shown that the Si/SiC devices have the potential to operate with an off-state leakage current as low as the SOI device. However, the low-side resistance of the SOI LDMOSFET is smaller in value and less sensitive to temperature, outperforming both Si/SiC devices. Conversely, under high-side configurations, the Si/SiC transistors have resistances lower than that of the SOI at high substrate bias, and invariablewith substrate potential up to −200 V, which behaves similar to the bulk-Si LDMOS at 300 K. Furthermore, the thermal advantage of the Si/SiC over other structures is demonstrated by using a rectanglepower pulse setup in TechnologyComputer-Aided Design simulations.

The Impact of Tunnel FET on Heavy Ion Induced Transient Effect

The heavy ion induced response in Tunnel FET (TFET) is discussed by comparing to that in conventional MOSFET using device simulation. It was confirmed that both shorter transient current pulse and smaller collected charge were observed in TFET due to suppression of the parasitic bipolar effects. Introduction One of the detrimental problems with CMOS devices in radiation environments, such as space and around the nuclear reactors, is single event phenomena (SEP). When a high-energy particle irradiates to the device, electron-hole pairs are generated along the ion-track by ionization effect, and they can create a sufficient transient current to cause an incorrect device response (single event transient). Silicon-on-insulator (SOI) technology had been developed to reduce SEP, because the sensitive region was limited to the individual transistors isolated from the substrate. However, the reliability issue is more sensitive on a higher performance CMOS device with the small device size, thin active region and lower applying voltage1). In case of conventional n-type SOI-MOSFET, the generated electrons in channel region are drifted to drain region by applying drain bias. However, the generated holes remain in the channel region due to the source/drain-channel barrier, and they degrade the source-channel potential barrier. Therefore the electrons in source region are injected to channel, and that creates a large current between source and drain. These phenomena are known as parasitic bipolar effects2). The effects are more enhanced in smaller size devices. In this study, we focused TFET as a radiation hardened device. The TFET has been developed to improve the sub-threshold slope, and is consisted by p-i-n type, as source-channel-drain region, with applying reverse bias. So it is expected that the radiation induced electrons and holes in channel region are drifted to drain and source, respectively, and that the parasitic bipolar effects can be reduced by TFET. We evaluated the heavy-ion induced transient current and collected charge in conventional FET and TFET, and also discussed the single event transient on TFET CMOS devices. Simulation Model Figure (a) shows the cross section of the each SOI device, conventional MOSFET and TFET. We calculated heavy-ion induced transient current in these devices using a 2D device simulator. We set the heavy-ion with the LET of 10 MeVcm2/mg strikes to the center of the channel region in each OFF-state (V G = 0 V, V D = 1.5 V) device with normal incidence. In this case, the amount of radiation induced generation charge is 52 fC in the active layer (SOI region). Result Figure (b) shows the simulated results of transient current and collected charge, the time integral of the current, of each device. On the results of conventional MOSFET, the decay rate of transient current is much slower than the TEFT, and it is confirmed that the amount of collecting charge is saturated with about 500 fC, about 10 times as much as generated charges. It is considered that the phenomena are caused by the parasitic bipolar effect. On the other hand, in TFET device, the transient current reduces steeply and the collected charge is saturated with the same value of generated one. From these results, it was confirmed that the radiation induced collected charge can be reduced significantly using TFET. We also evaluated the change of band diagram in each device with time after irradiation. In the results of conventional MOSFET, the source-channel potential barrier is changed to almost zero by irradiation due to the holes stored in the channel region. In the case of TFET, it is found that the band diagram in not changed by irradiation. That indicates the generated electrons and holes can escape rapidly from the channel region due to the asymmetric source/drain doping structure in TFET. From these results, we confirmed that the parasitic bipolar effects could be eliminated using TFET. Acknowledgement This work is supported by VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with Synopsys, Inc. Reference 1) P. E. Dodd, et al.,”SEU-Sensitive volumes in Bulk and SOI SRAMs From First-Principles Calculations and Experiments” IEEE Trans. Nucl. Sci., Vol. NS-48, pp. 1893-1903. (2001) 2) V. Ferlet-Cavrois, et al., “Statistical Analysis of the Charge Collected in SOI and Bulk Devices Under Heavy lon and Proton Irradiation—Implications for Digital SETs” IEEE Trans. Nucl. Sci. Vol. 53, No. 6, pp. 3242-3252. (2006) 3) D. Kobayashi, et al., “Analytical Expression for Temporal Width Characterization of Radiation-Induced Pulse Noises in SOI CMOS Logic Gates” in proceedings of IEEE CFP09RPS-CDR 47th Annual International Reliability Physics Symposium, Montreal (2009) Figure 1

Loss reduction of silicon-on-insulator waveguides for deep mid-infrared applications.

We report that propagation loss of optical waveguides based on a silicon-on-insulator (SOI) material platform can be greatly reduced. Our simulations show that the loss, including SiO2 absorption and substrate leakage, but no scattering loss, is 0.024 and 0.53dB/cm in the deep mid-infrared at 4.8 and 7.1μm wavelengths, where the material absorption in SiO2 is 100 and 1000dB/cm, respectively. The loss becomes negligible, compared to scattering loss in Si waveguides. This is enabled by using the TE10 mode in a pedestal waveguide. We also show that the TE10 mode can be excited in the proposed waveguide by the fundamental mode with a coupling efficiency of >94%. Low propagation loss, high coupling efficiency, and fabrication-friendly design would make it promising for practical use of SOI devices in the deep mid-infrared.

Application of Scanning Capacitance Microscopy on SOI device with wafer edge low yield pattern

As semiconductor technology keeps scaling down, many advanced technology and process were applied in the semiconductor process. Especially for the application of IOT (internet of thing) technology, the low leakage and low power consumption product was the key component for this kind of application. SOI (Silicon-On-Insulator) wafer process is one of the advanced and important branches of the semiconductor manufacturing process. Its intrinsic advantage, low leakage and lower power consuming make it very suitable for personal communication device and IOT which match well with the application requirement. As is well known the SOI wafer is different form the normal bulk silicon wafer. The active sits on the silicon oxide insulator, which makes the final device separate from the substrate. Basically, all of the devices are floating on a nonconductive oxide layer. It comes with many challenges for process and analysis as compared with the conventional bulk silicon process.The most conventional analysis method is not applicable in the SOI device such as the PVC (passive voltage contrast) and current image methodology which are a very powerful and important in the failure analysis.In this paper, scanning capacitance is successfully used as the substitution of the PVC method. The SCM (Scanning Capacitance Microscopy) is a complicated process. Since all of the abnormality or physical change will affect the measured capacitance, then the capacitance signal will theoretically has many information with itself, including open, short and leakage. Through the detailed study, the contact level top-down SCM was successfully applied on the SOI unit. By proper setting of SCM bias condition, it can not only visualize the possible leaky location but also can reveal the possible path. Further nanoprobing and TEM (Transmission Electron Microscopy) have confirmed the SCM analysis.

An experimental study of solid source diffusion by spin on dopants and its application for minimal silicon-on-insulator CMOS fabrication

Solid source diffusions of phosphorus (P) and boron (B) into the half-inch (12.5 mm) minimal silicon (Si) wafers by spin on dopants (SOD) have been systematically investigated and the physical-vapor-deposited (PVD) titanium nitride (TiN) metal gate minimal silicon-on-insulator (SOI) complementary metal–oxide–semiconductor (CMOS) field-effect transistors (FETs) have successfully been fabricated using the developed SOD thermal diffusion technique. It was experimentally confirmed that a low temperature oxidation (LTO) process which depresses a boron silicide layer formation is effective way to remove boron-glass in a diluted hydrofluoric acid (DHF) solution. It was also found that top Si layer thickness of SOI wafers is reduced in the SOD thermal diffusion process because of its consumption by thermal oxidation owing to the oxygen atoms included in SOD films, which should be carefully considered in the ultrathin SOI device fabrication. Moreover, normal operations of the fabricated minimal PVD-TiN metal gate SOI-CMOS inverters, static random access memory (SRAM) cells and ring oscillators have been demonstrated. These circuit level results indicate that no remarkable particles and interface traps were introduced onto the minimal wafers during the device fabrication, and the developed solid source diffusion by SOD is useful for the fabrication of functional logic gate minimal SOI-CMOS integrated circuits.

Quasi-Schottky-Barrier UTBB SOI MOSFET for Low-Power Robust SRAMs

This paper presents a low-power robust static random access memory (SRAM) using a novel quasi-Schottky-barrier ultrathin body and ultrathin buried oxide (UTBB) silicon-on-insulator (SOI) device. In the proposed device, the drain terminal is highly doped and a metallic source terminal is used. Given the proposed structure, asymmetric characteristics will be achieved according to the drain–source bias voltage ( ${V}_{\text {DS}})$ . These characteristics of the proposed device are extensively analyzed and compared with a conventional symmetric UTBB SOI device. The asymmetry nature of the proposed device will lead to the mitigated read–write conflict of the 6T-SRAM cell. The simulation results show a leakage reduction of 18% at ${V}_{\text {DD}} = 1$ V in comparison with the 6T-SRAM cell realized by conventional symmetric UTBB SOI device. Furthermore, in comparison with the conventional 6T-SRAM, the realized cell shows a 54% improvement in read static noise margin, 6.6% higher write margin, and $3.1\times $ faster write at the cost of a longer access time. To achieve a practical read access time, we utilize split bitline approach.

Fabricating with crystalline Si to improve superconducting detector performance

We built and measured radio-frequency (RF) loss tangent, tan δ, evaluation structures using float-zone quality silicon-on-insulator (SOI) wafers with 5 μm thick device layers. Superconducting Nb components were fabricated on both sides of the SOI Si device layer. Our main goals were to develop a robust fabrication for using crystalline Si (c-Si) dielectric layers with superconducting Nb components in a wafer bonding process and to confirm that tan δ with c-Si dielectric layers was reduced at RF frequencies compared to devices fabricated with amorphous dielectrics, such as SiO2 and SixNy, where tan δ ∼ 10-3. Our primary test structure used a Nb coplanar waveguide (CPW) readout structure capacitively coupled to LC resonators, where the capacitors were defined as parallel-plate capacitors on both sides of a c-Si device layer using a wafer bonding process with benzocyclobutene (BCB) wafer bonding adhesive. Our control experiment, to determine the intrinsic tan δ in the SOI device layer without wafer bonding, also used Nb CPW readout coupled to LC resonators; however, the parallel-plate capacitors were fabricated on both sides of the Si device layer using a deep reactive ion etch (DRIE) to access the c-Si underside through the buried oxide and handle Si layers in the SOI wafers. We found that our wafer bonded devices demonstrated F· δ = (8 ± 2) × 10-5, where F is the filling fraction of two-level states (TLS). For the control experiment, F· δ = (2.0 ± 0.6) × 10-5, and we discuss what may be degrading the performance in the wafer bonded devices as compared to the control devices.