Abstract
This paper analyses the effect of employing an Si on semi-insulating SiC (Si/SiC) device architecture for the implementation of 600-V LDMOSFETs using junction isolation and dielectric isolation reduced surface electric field technologies for high-temperature operations up to 300 °C. Simulations are carried out for two Si/SiC transistors designed with either PN or silicon-on-insulator (SOI) and their equivalent structures employing bulk-Si or SOI substrates. Through comparisons, it is shown that the Si/SiC devices have the potential to operate with an off-state leakage current as low as the SOI device. However, the low-side resistance of the SOI LDMOSFET is smaller in value and less sensitive to temperature, outperforming both Si/SiC devices. Conversely, under high-side configurations, the Si/SiC transistors have resistances lower than that of the SOI at high substrate bias, and invariablewith substrate potential up to −200 V, which behaves similar to the bulk-Si LDMOS at 300 K. Furthermore, the thermal advantage of the Si/SiC over other structures is demonstrated by using a rectanglepower pulse setup in TechnologyComputer-Aided Design simulations.
Highlights
T HE reduced surface electric field (RESURF) principle has been widely used for Si-based lateral power transistors, enabling them to operate one-step closer to the ideal switch that features infinite electrical conductivity or resistivity when turned ON or OFF
A nearly linear voltage drop can be seen along the x-direction of the drift region of each device, which results from the vertical depletion induced by the SOI layout or P-N pairs
The blocking voltage in this case is governed in part by the thickness of the FOX, which resembles the criteria for the BOX in the traditional SOI structures [22]
Summary
T HE reduced surface electric field (RESURF) principle has been widely used for Si-based lateral power transistors, enabling them to operate one-step closer to the ideal switch that features infinite electrical conductivity or resistivity when turned ON or OFF. As for the bulk-Si-like Si/SiC, impurity concentrations of the N drift and P buried are determined based upon the triple RESURF principle [20], while the P-substrate doping is decided following the rule for lateral SiC-on-SI SiC power transistors [25] These configurations result in the drift regions of both devices having similar doses of about 3 × 1012 cm−2 [20] but they differ in doping concentration (cm−3) owing to dissimilar Si layer thickness. The Si/SiC wafers with P-type silicon exhibits leakage lower than that of the bulk-Si reference [21], indicating that the bonded substrate has a device-quality Si layer with good electrical insulation properties, and that the leakage is likely to be induced by the depletion or inversion in the very low-doped N-type region [21] This phenomenon may affect the electrical characteristics of the two transistors in Fig. 2 differently as they are designed on a Si region with opposite doping types. It is worth noting that this Si/SiC interface charge will vary according to the wafer bonding process and subsequent annealing, which will affect device performance
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