Silicon-on-insulator Devices Research Articles

SOI power devices

This paper provides an introduction to silicon-on-insulator (SOI) technology and the operating principles of high-voltage SOI devices, reviews the performance of the available SOI switching devices in comparison with standard silicon devices, discusses the reasoning behind the use of SOI technology in power applications and covers the most advanced novel power SOI devices proposed to date. The impact of SOI technology on power integrated circuits (PICs) and the problems associated with the integration of high-voltage and low-voltage CMOS are also analysed.

On the design and fabrication of novel lateral bipolar transistor in a deep-submicron technology

The performance of a npn Lateral Bipolar Transistor (LBJT), based on a minimally modified submicron MOSFET without gate oxide, was studied by means of simulations and measurements on fabricated devices. Large-tilt angle, single-sided implants were successfully used to control the breakdown voltage by tailoring an asymmetric collector doping profile and providing a lightly doped region on the collector side to increase the breakdown voltage. This was accomplished by using a base/gate pedestal as the mask for the large-tilt angle, single sided implantation in a self-aligned fashion. The individual collector–base and emitter–base junctions were found to be of excellent quality but, as expected due to the lack of carrier confinement in the base of devices built on bulk silicon, the common emitter current gain was lower than one. Two options enhancing the device performance were studied using simulators: building the LBJT on Silicon-on-Insulator (SOI) or introducing SiGe into the base. The SOI device promises to provide better performance and ease of processing when compared to the SiGe base device.

A simple method to determine the floating-body voltage of SOI CMOS devices

A technique to extract the off-state floating-body (FB) voltage of silicon-on-insulator (SOI) CMOS devices is presented. The bias dependent S-parameter measurements of a single standard FB SOI device and its equivalent circuit, along with the capacitance-voltage (C-V) measurements between the drain and source of the same device, are used to determine the FB voltage. No special test structure design is needed. The technique proposes a method for the extraction of the parasitic source, drain, and gate resistances. Using the technique, FB voltage in excess of 0.4 V is measured in a partially depicted (PD) NMOS device at drain voltage of 2.5 V and zero gate voltage.

Studies of charge collection mechanisms in SOI devices using a heavy-ion microbeam

Transient currents induced in silicon-on-insulator (SOI) devices by high energy-carbon or oxygen ions were evaluated using a focused ion microbeam and a wide bandwidth measurement system. The total amount of collected charge in the SOI pn junction with the 5.7μm thick top Si layer was found to be less than that in pn junctions fabricated in bulk Si. The charge collection was estimated to be limited in the top Si layer of the SOI devices. These findings give experimental evidence that SOI devices have higher resistance to soft error than conventional bulk Si devices.

Recombination current modeling and carrier lifetime extraction in dual-gate fully-depleted SOI devices

The typical behavior of the recombination current in fully-depleted silicon-on-insulator (SOI) PIN diodes including gate-all-around and double-gate configurations is investigated. An excess forward current is measured when carrier recombination occurs in the whole body of the device. A novel recombination-box model is proposed, validated by two-dimensional (2-D) simulation, and used to extract the carrier recombination rate. The physical origin of carrier recombination in fully-depleted structures is discussed in terms of volume and/or surface contributions.

Metastability of SOI CMOS latches

An analysis of the metastability of silicon-on-insulator (SOI) complementary metal-oxide-silicon (CMOS) latches is presented, using partially-depleted SOI devices with various body-connection topologies and an unbuffered latch. The metastability window, resolution time and time interval between the clock edge and the time t meta are evaluated as functions of power supply and the type of body-connection topology. Simulations using SOISPICE show improved metastability behaviour for SOI specific body-connection topologies.

Modelling of self-heating effect in thin SOI and Partial SOI LDMOS power devices

This paper presents a comprehensive 2-D and 1-D study of the self-heating effect in thin Silicon-on-Insulator (SOI) and Partial SOI LDMOS power devices. A simple 1-D self-heating model based on a PSPICE RC thermal circuit which accounts for the temperature rise in on-state, transient and short-circuit conditions is developed. Unlike previous 1-D modelling attempts for SOI devices, our model takes into account the feedback effect of the local device temperature on the thermal conductivity and specific heat through an equivalent electrical RC network consisting of voltage controlled resistors and capacitors. The 1-D model is thoroughly assessed against extensive 2-D thermal simulations performed using the SILVACO-ATLAS device simulator and the results indicate an excellent agreement in all operating conditions. Furthermore, an accurate comparison between the thin SOI and Partial SOI devices is carried out.

Thermal and package performance limitations in LDMOSFET's for RFIC applications

This paper presents a systematic study of the limitations imposed by thermal and packaging considerations on radio-frequency (RF) performance of Si bulk and silicon-on-insulator (SOI) lateral DMOSFET's (LDMOSFET's). Several bulk and SOI devices are studied with the help of measurements as well as two-dimensional device simulations incorporating electrothermal models. Model parameters are extracted and used in circuit simulators to perform RF characterization of these devices. Further, a new three-region theory for the LDMOSFET is discussed and used to evaluate the static and RF performance of the devices in a nonisothermal environment. This paper shows that the package plays an important role in RF performance of SOI and bulk devices due to self-heating effects within the device. A detailed DC and RF performance evaluation is presented. Significant drift is observed in RF performance of bulk and SOI devices due to self-heating considerations. The physical understanding of these thermal effects within the device can facilitate the design of better packages for bulk and SOI devices.

Carrier lifetime extraction in fully depleted dual-gate SOI devices

A new method for extracting the carrier recombination lifetime in dual-gate silicon-on-insulator (SOI) structures is proposed. The experiment, model, and numerical simulations indicate that an excess forward current is obtained when carrier recombination occurs in the whole film volume.

Measurement of carrier generation lifetime in SOI devices

This paper presents a new, simple method of measuring the generation lifetime in SOI (silicon-on-insulator) MOSFETS. Lifetime is extracted from the transient characteristics of MOSFET subthreshold current. Using this technique, generation lifetime was mapped across finished SIMOX (separation by implantated oxygen) wafers, BESOI (bonded and etchedback SOI) wafers, and UNIBOND wafers. BESOI material evaluated in this study had about seven times longer effective generation lifetime than SIMOX material and the three types of the SOI wafers are shown to have a lifetime variation of ±20% across four inch wafers. The generation lifetime was also found to depend on the device fabrication process.

Measurement of buried oxide thermal conductivity for accurate electrothermal simulation of SOI device

Finite element simulations demonstrate that the thermal conductivity of the buried oxide is an important parameter for the modeling of the thermal behavior of silicon-on insulator (SOI) devices. There is uncertainty about the conductivity of different forms of SiO/sub 2/, particularly that of buried oxides. This paper presents a novel approach to measure this conductivity, using structures that are compatible with standard bipolar or CMOS processes. Thermal conductivity values of 0.66 and 0.82 W/mK, respectively, were found for 300-nm BESOI and 420-nm SIMOX oxides at room temperature. The measured variations of thermal conducitivity with temperature agree well with bulk SiO/sub 2/ behavior. Better agreement between measurement and finite element simulation of MOSFET thermal resistance is obtained by using these extracted thermal conductivity values. It is also shown that the role of the silicon substrate in determining the thermal resistance of the device can be calculated using a simple analytical model. This is important when one wishes to calculate accurately individual thermal resistances of transistors in a given circuit.

The Realization of Silicon‐on‐Insulator Utilizing Trench‐before‐Bond and Polish Stop Technology

Silicon‐on‐insulator (SOI) structures comprised of fully dielectrically isolated device wells have been fabricated, utilizing a trench‐before‐bond process to create polish stops. The SOI layers have thicknesses between 1.5 and 3.0 μm with uniformities of ±5% across a 500 μm device well, which would not be achievable with grind and polish techniques only. The SOI layer thickness was defined by the depth of isolation trenches, formed prior to bonding, which acted as the final SOI polish stops. The prebond planarization process is very dependent on polish conditions used. It was found that opting for a polishing slurry with a lower pH value allowed the planarization of polysilicon layers. The polish process resulted in refill layers that could be bonded without pattern‐related voids. A similar polishing process also displayed minimal dishing in the final SOI device wells, as the variability of the polishing process is limited by the polish stops. The trench‐before‐bond process minimizes the risk of oxidation‐induced defects, arising from SOI isolation trenches, as these are refilled prior to bonding. It also offers a cheaper alternative to epitaxial growth on SIMOX substrates as a means of obtaining layers within this thickness range.

SOI for digital CMOS VLSI: design considerations and advances

This paper reviews the recent advances of silicon-on-insulator (SOI) technology for complementary metal-oxide-semiconductor (CMOS) very-large-scale-integration memory and logic applications. Static random access memories (SRAMs), dynamic random access memories (DRAMs), and digital CMOS logic circuits are considered. Particular emphases are placed on the design issues and advantages resulting from the unique SOI device structure. The impact of floating-body in partially depleted devices on the circuit operation, stability, and functionality are addressed. The use of smart-body contact to improve the power and delay performance is discussed, as are global design issues.

Leakage current models of thin film silicon-on-insulator devices

Thin film silicon-on-insulator (SOI) devices have an advantage of excellent isolation due to the buried oxide layer leading to reduced capacitance coupling and no latchup in complementary metal-oxide-silicon circuits compared with bulk silicon devices. Reduced junction area should lead to lower leakage for a given device. However, because of the buried oxide, stress is built up in the Si island during isolation processes, especially near the island edges, inducing new kinds of leakage currents, which are not observed in bulk silicon devices. This letter proposes five leakage current models of the partially depleted SOI devices, identifies their origins, and suggests methods to prevent each type.

Failure Analysis Using Voltage Contrast and Ebic

AbstractAs ULSI device critical dimensions continue to shrink to submicron sizes, electron microscopy techniques such as electron beam induced current (EBIC) and voltage contrast are finding more applications towards pinpointing failure sites for subsequent cross sectioning or deprocessing. In addition to the traditional use of EBIC for junction delineation, EBIC has been applied to locate leakage sites in capacitor structures and silicon-on-insulator (SOI) devices as well. Similarly, voltage contrast has been applied to identify single or multiple opens in via chains which consist of thousands of vias. In addition to a brief revisit of the basic principles of EBIC and voltage contrast, focus will be placed on the application of EBIC and voltage contrast in failure analysis of semiconductor devices. Examples of using voltage contrast combined with precision cross section focused ion beam (XFIB) for identifying the failure mechanism of 0.8μm vias will be presented. Also, the use of EBIC for identifying leakage sites in SOI and bipolar devices and subsequent FIB/scanning electron microscopy (SEM) analysis will be presented.

A traveling-wave model for optimizing the bandwidth of p-i-n photodetectors in silicon-on-insulator technology

The paper presents an efficient design method for predicting the bandwidth of traveling-wave photodetectors (TWPD's) in silicon-on-insulator (SOI) coplanar technology. First the transmission-line parameters describing the propagation mechanism in the structure are computed up to optical frequencies, as a function of the geometry and of the carrier concentrations. Next, a traveling-wave equivalent model is derived, which takes into account the propagation mechanism of the optical beam into the silicon active area and the carriers transit time in the p-i-n junction. Using the model enables us to theoretically optimize the radio-frequency output power of the p-i-n structure over a wide frequency range by a judicious choice of the optical and RF loads at the accesses of the equivalent opto-electronic coupler formed by the TWPD. SOI coplanar TWPD's supporting a traveling optical wave exhibit an improvement of the 3-dB bandwidth by more than 50% compared with uniformly illuminated SOI PD's or with GaAs TWPD's of same geometry and the bandwidth-efficiency product can be enhanced by achieving adequate reflection conditions for the optical signal at the ends of the SOI device.

Introduction to Silicon On Insulator materials and devices

From a theoretical viewpoint, Silicon On Insulator (SOI) is the most attractive technology for low-voltage ULSI circuits. A strict condition for competing effectively with bulk silicon is the understanding of material properties, fabrication techniques, and device operation. This paper reviews the main advantages of SOI devices, the various technological approaches, the more or less exotic family of SOI devices and the special mechanisms involved in the operation of thin SOI MOSFETs.

Experimental study of nonstationary electron transport in sub-0.1 μm metal–oxide–silicon devices: Velocity overshoot and its degradation mechanism

We have experimentally studied the electron velocity overshoot and the mechanism of its degradation in the inversion layer of sub-0.1 μm metal–oxide–silicon (MOS) field-effect transistors. Both silicon-on-insulator (SOI) and bulk structures were studied. At low transverse electric fields, that is, for low carrier densities in SOI devices under low gate drive conditions, it is possible to achieve electron velocity overshoot due to nonstationary transport in the sub-0.1 μm region. However, it is very difficult in MOS structures to improve electron velocity at high surface electron densities because of the reduced electron mobility in high transverse fields. Moreover, the surface electron density of MOS structures is reduced when a low channel impurity concentration is chosen to improve low field mobility; this results from the expanded inversion layer width. These results indicate the physical limitations of scaled MOS structures with regards to the realization of higher current capabilities.

Reduced plasma-induced chaging damage in SOI MOSFETs

The impact of plasma-induced charging damage on dielectric breakdown was examined on both bulk silicon and Silicon-On-Insulator (SOI) MOSFETs for different conductors for various antenna area ratios. It was found that the Time-Zero Dielectric Breakdown (TZDB) distributions for the SOI devices were less dependent on antenna ratio and less susceptible to antenna charging damage than bulk silicon devices. This behavior is because the current path for charging damage is not available in SOI, since each silicon island is isolated from others. NMOS and PMOS devices behaved similarly and no difference was observed between SOI devices fabricated on SIMOX and bonded silicon substrates.

Measurement of the Breakdown Voltage of Lateral Power Metal-Oxide-Semiconductor Field-Effect-Transistors on a Silicon-on-Insulator Film with Varying the Surface Design around the Gate Region

The gate structure dependence of the blocking capability of lateral power metal-oxide-semiconductor field-effect-transistors (MOSFETs) on a silicon-on-insulator (SOI) film is investigated. Experimental results of the breakdown voltage with varying the gate electrode and gate oxide lengths are presented, and are compared with those of the devices fabricated on a n-type substrate. The breakdown voltage of the SOI devices is insensitive to the surface design around the gate structure, which is quite different from that of the devices on the n-type substrate.