Silicon Nanowire Transistors Research Articles

Bismuth-catalyzed n-type doping and growth evolution of planar silicon nanowires

Guided growth of silicon nanowires (SiNWs) into precise locations, via an in-plane solid–liquid–solid (IPSLS) mechanism, is a key basis for scalable integration of SiNW-based electronics, but an effective n-type doping has not yet been accomplished. In this work, we report a bismuth (Bi) catalyzed and doped growth of IPSLS SiNWs, where the incorporation of Bi atoms gives rise to efficient n-type doping, as confirmed by electron dispersion analysis and transfer properties of SiNW transistors. Interestingly, a rich geometry evolution is observed during the Bi-catalyzed planar growth, which evolves from discrete islands to continuous island chains and to uniform segments, prior to a final droplet collapsing/flattening at the end. A growth model has been established to address this peculiar phenomenon, emphasizing the impact of surface/interface tensions on the stability of the leading catalyst droplet. These results provide a solid basis for the construction of more advanced complementary SiNW logics and electronics.

A new factor for fabrication technologies evaluation for silicon nanowire transistors

This paper reviews the fabrication technologies of silicon nanowire transistors (SiNWTs) and rapidly development in this area, as this paper presents various types of SiNWT structures, development of SiNWT properties and different applications until nowadays. This research provides a good comparison among fabrication technologies of SiNWTs depending on a new factor DIF, this factor depends on the size of channel and power consumption in channel. As a result of this comparison, the best technology to use in the future to fabricate silicon nano transistors for future ICs is AFM nanolithography.

Superior subthreshold characteristics of gate-all-around p-type junctionless poly-Si nanowire transistor with ideal subthreshold slope

Junctionless p-type polycrystalline silicon (poly-Si) nanowire (NW) transistor with ideal subthreshold slope (SS) is successfully demonstrated by a gate-all-around channel structure and improved fabrication processes with highly suppressed grain boundary defects in the poly-Si. The fabricated devices, whose NW width is 9.6 nm, exhibit nearly ideal SS of 60 mV dec−1 at room temperature. Furthermore, relatively high field effect mobility, small device-to-device SS variations and negligible temperature dependence are observed, indicating the device is promising for future three-dimensional integration.

Intrinsic plasticity of silicon nanowire neurotransistors for dynamic memory and learning functions

Neuromorphic architectures merge learning and memory functions within a single unit cell and in a neuron-like fashion. Research in the field has been mainly focused on the plasticity of artificial synapses. However, the intrinsic plasticity of the neuronal membrane is also important in the implementation of neuromorphic information processing. Here we report a neurotransistor made from a silicon nanowire transistor coated by an ion-doped sol–gel silicate film that can emulate the intrinsic plasticity of the neuronal membrane. The neurotransistors are manufactured using a conventional complementary metal–oxide–semiconductor process on an 8-inch (200 mm) silicon-on-insulator wafer. Mobile ions allow the film to act as a pseudo-gate that generates memory and allows the neurotransistor to display plasticity. We show that multiple pulsed input signals of the neurotransistor are non-linearly processed by sigmoidal transformation into the output current, which resembles the functioning of a neuronal membrane. The output response is governed by the input signal history, which is stored as ionic states within the silicate film, and thereby provides the neurotransistor with learning capabilities. A neurotransistor made from a silicon nanowire transistor coated by an ion-doped sol–gel silicate film can emulate the intrinsic plasticity of the neuronal membrane.

Effective gate length model for asymmetrical gate-all-around silicon nanowire transistors

Effective gate length model for asymmetrical gate-all-around silicon nanowire transistors

Width dependence of drain current and carrier mobility in gate-all-around multi-channel polycrystalline silicon nanowire transistors with 10 nm width scale

The width dependences of characteristics of gate-all-around (GAA) polycrystalline silicon (poly-Si) transistors with 10 nm scale width were systematically investigated. The fabricated 14 nm wide GAA multi-channel poly-Si transistors exhibited excellent electrical properties including small subthreshold swing (105 mV/decade) and high Ion/Ioff ratio (∼108). Drain current normalized to effective width increases with decreasing nanowire width. It is found by the advanced split capacitance–voltage technique that both inversion carrier density and mobility are enhanced in the narrower nanowires and that the corner effect plays an important role in the drain current enhancement.

Channel Length-Based Comparative Analysis of Temperature and Electrical Characteristics for SiNWT and GeNWT

This paper investigates the temperature sensitivity and electrical characteristics of Silicon Nanowire Transistor (SiNWT) and Germanium Nanowire Transistor (GeNWT) depending on variable channel length (Lg). It also studies the possibility of using them as a temperature nanosensor. The MuGFET simulation tool was exploited to investigate the characteristics of the considered nanowire transistors. Current-voltage characteristics with different values of temperature with channel length [Lg = 25, 45, 65, 85 and 105 nanometer (nm)], were simulated. MOS diode mode connection suggested measuring the temperature sensitivity of SiNWT and GeNWT too. Three (3) electrical characteristics namely; (i) Subthreshold Swing (SS), (ii) Threshold voltage (VT), and (iii) Drain-induced barrier lowering (DIBL) were evaluated and compared for both NWTs. The obtained results show that SiNWT achieved a better temperature sensitivity with channel length range between 25 nm to 105 nm at operation voltage (VDD) range 1 V to 5 V nm. It is very clear that the temperature sensitivity increased remarkably by increasing channel length for both of SiNWT and GeNWT as well, but in SiNWT the sensitivity is more steady compared to GeNWT that showing less sensitivity. Moreover, SiNWT shows better result in terms of electrical performance metrics for various channel length at T = 300 K comparing with GeNWT.

Optimization of n-MOS 6T Nanowire SRAM Bit Cell Based on Nanowires Ratio of SiNWTs

In nowadays technology, the primary memory structure widely used in many digital circuit applications is a six transistor (6T) Static Random Access Memory (SRAM) bit cell. The main reason for minimizing memory bit cell to nanodimensions is to provide the SRAM integrated circuits (ICs) with the possible largest memory size per one chip, and the main unit in 6T SRAM bit cell is the MOSFET. One of the new MOSFET structures that overcome conventional MOSFET structure problems under minimization towards nanodimension is the silicon nanowire transistor (SiNWT). This study is the first to explore and optimize the nanowire ratio of driver to load (KD/KL) for a six n-channel SiNWT-based SRAM bit cell. The MuGFET simulation tool has been used to calculate the output characteristics of each transistor individually, and then these characteristics are implemented in the MATLAB software to produce the final static butterfly and current characteristics of nanowire 6T-SRAM bit cell. The demonstration of the driver to load transistors’ nanowires ratio optimizations of nanoscale n-type SiNWT-based SRAM bit cell has been discussed. In this research, the optimization of KD/KL will strongly depend on inflection voltage and high and low noise margins (NMs) of butterfly characteristics. The improvement of NMs of butterfly characteristics has been done by increasing the drain current (Ids) of the driver transistor. Also, the optimization in principle will depend on whether NMs are equal and high, and the inflection voltage (Vinf) is near to Vdd/2 values as possible. These principles have been used as limiting factors for optimization. The results show that the optimization strongly depends on the nanowire ratio, and the best ratio was KD/KL 4. The increase in KD/KL leads to a continuous increase in NMH, acceptable NML and low percentage increment of static power consumption (ΔP %) at KD/KL 4.

Multi-terminal ionic-gated low-power silicon nanowire synaptic transistors with dendritic functions for neuromorphic systems.

Neuromorphic computing systems have shown powerful capability in tasks, such as recognition, learning, classification and decision-making, which are both challenging and inefficient in using the traditional computation architecture. The key elements including synapses and neurons, and their feasible hardware implementation are essential for practical neuromorphic computing. However, most existing synaptic devices used to emulate functions of a single synapse and the synapse-based networks are more energy intensive and less sustainable than their biological counterparts. The dendritic functions such as integration of spatiotemporal signals and spike-frequency coding characteristics have not been well implemented in a single synaptic device and thus play an imperative role in future practical hardware-based spiking neural networks. Moreover, most emerging synaptic transistors are fabricated by nanofabrication processes without CMOS compatibility for further wafer-scale integration. Herein, we demonstrate a novel ionic-gated silicon nanowire synaptic field-effect transistor (IGNWFET) with low power consumption (<400 fJ per switching event) based on the standard CMOS process platform. For the first time, the dendritic integration and dual-synaptic dendritic computations (such as "Add" and "Subtraction") could be realized by processing frequency coded spikes using a single device. Meanwhile, multi-functional characteristics of artificial synapses including the short-term and long-term synaptic plasticity, paired pulse facilitation and high-pass filtering were also successfully demonstrated based on 40 nm wide IGNWFETs. The migration of ions in polymer electrolyte and trapping in high-k dielectric were also experimentally studied in-depth to understand the short-term plasticity and long-term plasticity. Combined with statistical uniformity across a 4-inch wafer, the comprehensive performance of IGNWFET demonstrates its potential application in future biologically emulated neuromorphic systems.

Impacts of NBTI and hot-carrier stress on silicon nanowire transistor characteristics

Following the downscaling road map for planar metal–oxide–semiconductor field-effect transistors, non-planar (three-dimensional) multiple-gate architectures are becoming essential for the ultimate scaling of complementary metal–oxide–semiconductor devices. Gate-all-around (nanowire) field-effect transistors have proven to be the most suitable below-22 nm technology nodes. Hence the reliability of these devices is of great concern. Negative-bias temperature instability (NBTI) and hot-carrier degradation (HCD) are the key device reliability issues that exhibit some different features at nanoscale. In this work, the NBTI reliability issues of p-channel gate-all-around silicon nanowire transistors (SNWTs) under direct-current and alternating-current stress were investigated. When stressed, the NBTI behavior in SNWTs showed fast initial degradation, quick degradation saturation and then a special recovery behavior. Along with that, the effects of hot-carrier stress on n-channel SNWTs were studied. Due to the surrounded gate structure, it was observed that the effects of HCD were significant in the nanowire transistors.

Characterization of silicon nanowire transistor

This paper analyses the temperature sensitivity of Silicon Nanowire Transistor (SiNWT) depends on the diameter (D.ch) of channel. In addition, it also investigates the possibility of utilizing SiNWT as a Nano- temperature sensor. The MuGFET simulation tool has been utilized to conduct a comprehensive simulation to evaluate both electrical and temperature characteristics of SiNWT. Current-voltage characteristics with different values of temperature and with a varying diameter of the Nano wire channel (D.ch = 80, 40, 20 and 10 nm), were simulated. Diode operating mode connection of the transistor is suggested for measuring the temperature sensitivity of SiNWT. As simulation results demonstrated, the best temperature sensitivity was occurred at lower temperature with increasing the channel diameter. We also illustrate the impact of varying temperature and channel diameter on electrical characteristics of SiNWT including, Subthreshold Swing (SS), Threshold voltage (V.th), and Drain-induced barrier lowering (DIBL), which were proportionally increased with the operating temperature.

Optically tunable feedback operation of silicon nanowire transistors

In this study, we present an optically tunable feedback field-effect transistor (FBFET) with two independent gates and a p+-i-n+ silicon nanowire. Because of the feedback operation, the FBFET features extremely steep switching characteristics with subthreshold swings <4 mV dec−1, and it can be reconfigured as a p- or n-type transistor by controlling the gate-voltage biases. When the FBFET is exposed to a He–Ne laser beam (λ = 633 nm), photogenerated carriers accumulate in the potential wells and reduce the potential-barrier height. The optically tunable feedback operation is attributed to the lowering of the potential barrier caused by the light. The triggering voltages can be modulated according to illumination, even when feedback is being provided. This optically tunable transistor with excellent switching characteristics opens up possibilities for application in future optoelectronic devices.

Mobility of Circular and Elliptical Si Nanowire Transistors Using a Multi-Subband 1D Formalism

We have studied the impact of the cross-sectional shape on the electron mobility of n-type silicon nanowire transistors (NWTs). We have considered circular and elliptical cross-section NWTs including the most relevant multisubband scattering processes involving phonon, surface roughness, and impurity scattering. For this purpose, we use a flexible simulation framework, coupling 3D Poisson and 2D Schrodinger solvers with the semi-classical Kubo-Greenwood formalism. Moreover, we consider cross-section dependent effective masses calculated from tight binding simulations. Our results show significant mobility improvement in the elliptic NWTs in comparison to the circular one for both [100] and [110] transport directions.

Hydrodynamic modeling of electron transport in gated silicon nanowires transistors

We present a theoretical study of the low-field electron mobility in rectangular gated silicon nanowire transistors at 300 K based on a hydrodynamic model and the self-consistent solution of the Schrodinger and Poisson equations. The hydrodynamic model has been formulated by taking the moments of the multisubband Boltzmann equation, and closed on the basis of the Maximum Entropy Principle. It includes scattering of electrons with acoustic and non-polar optical phonons and surface roughness scattering.

Incorporation of Phosphorus Impurities in a Silicon Nanowire Transistor with a Diameter of 5 nm

Silicon nanowire (SiNW) is always accompanied by severe impurity segregation and inhomogeneous distribution, which deteriorates the SiNWs electrical characteristics. In this paper, a method for phosphorus doping incorporation in SiNW was proposed using plasma. It showed that this method had a positive effect on the doping concentration of the wires with a diameter ranging from 5 nm to 20 nm. Moreover, an SiNW transistor was assembled based on the nanowire with a 5 nm diameter. The device’s ION/IOFF ratio reached 104. The proposed incorporation method could be helpful to improve the effect of the dopants in the silicon nanowire at a nanometer scale.

Low-field electron mobility evaluation in silicon nanowire transistors using an extended hydrodynamic model

Silicon nanowires (SiNWs) are quasi-one-dimensional structures in which electrons are spatially confined in two directions and they are free to move in the orthogonal direction. The subband decomposition and the electrostatic force field are obtained by solving the Schrödinger–Poisson coupled system. The electron transport along the free direction can be tackled using a hydrodynamic model, formulated by taking the moments of the multisubband Boltzmann equation. We shall introduce an extended hydrodynamic model where closure relations for the fluxes and production terms have been obtained by means of the Maximum Entropy Principle of Extended Thermodynamics, and in which the main scattering mechanisms such as those with phonons and surface roughness have been considered. By using this model, the low-field mobility of a Gate-All-Around SiNW transistor has been evaluated.

Fabrication and DC/AC Characterization of 3-Terminal Ferromagnet/Silicon Spintronics Devices

CMOS and SOI technology compatible structures and devices are currently intensively investigated by many research groups, since various effects observed in such structures can be relatively easy implemented in electronic devices thereby expanding their functionality. The most promising is the research and development of spintronic devices, which will allow using both electron charge and spin degrees of freedom for transmission, storage and processing of information. In this work we report the fabrication process of 3-terminal (3-T) ferromagnet/silicon devices of two types. First is the planar Fe3Si/Si 3-T structure with 5 μm gap between closest ferromagnetic electrodes. Second is silicon nanowire back-gate transistor with Fe film source and drain synthesized on SOI substrate. Transport and magnetotransport properties of both devices are investigated.

Primary thermometry of a single reservoir using cyclic electron tunneling to a quantum dot

At the nanoscale, local and accurate measurements of temperature are of particular relevance when testing quantum thermodynamical concepts or investigating novel thermal nanoelectronic devices. Here, we present a primary electron thermometer that allows probing the local temperature of a single-electron reservoir in single-electron devices. The thermometer is based on cyclic electron tunneling between a system with discrete energy levels and the reservoir. When driven at a finite rate, close to a charge degeneracy point, the system behaves like a variable capacitor whose full width at half maximum depends linearly with temperature. We demonstrate this type of thermometer using a quantum dot in a silicon nanowire transistor. We drive cyclic electron tunneling by embedding the device in a radio-frequency resonator which in turn allows reading the thermometer dispersively. Overall, the thermometer shows potential for local probing of fast heat dynamics in nanoelectronic devices and for seamless integration with silicon-based quantum circuits.

Manipulation of random telegraph signals in a silicon nanowire transistor with a triple gate

Manipulation of carrier densities at the single electron level is inevitable in modern silicon based transistors to ensure reliable circuit operation with sufficiently low threshold-voltage variations. However, previous methods required statistical analysis to identify devices which exhibit random telegraph signals (RTSs), caused by trapping and de-trapping of a single electron. Here, we show that we can deliberately introduce an RTS in a silicon nanowire transistor, with its probability distribution perfectly controlled by a triple gate. A quantum dot (QD) was electrically defined in a silicon nanowire transistor with a triple gate, and an RTS was observed when two barrier gates were negatively biased to form potential barriers, while the entire nanowire channel was weakly inverted by the top gate. We could successfully derive the energy levels in the QD from the quantum mechanical probability distributions and the average lifetimes of RTSs. This study reveals that we can manipulate individual electrons electrically, even at room temperature, and paves the way to use a charged state for quantum technologies in the future.

Switchable‐Memory Operation of Silicon Nanowire Transistor

AbstractThe switchable‐memory operation of a feedback silicon nanowire transistor with a dual‐gate structure is demonstrated. The single transistor exhibits volatile memory characteristics with a retention time longer than 3600 s, as well as a switching capability with a subthreshold swing lower than 7 mV dec−1. A gate‐controlled memory window forms around a gate voltage of 0 V owing to the positive feedback loop in the channel region, allowing a program/erase endurance of more than 1000 cycles. The memory transistor, with switching capability, opens up the possibility of overcoming not only the scaling limit faced by conventional volatile memory but also the inherent drawback of the separation of the building blocks for memory and logic.