Superior subthreshold characteristics of gate-all-around p-type junctionless poly-Si nanowire transistor with ideal subthreshold slope

Abstract

Junctionless p-type polycrystalline silicon (poly-Si) nanowire (NW) transistor with ideal subthreshold slope (SS) is successfully demonstrated by a gate-all-around channel structure and improved fabrication processes with highly suppressed grain boundary defects in the poly-Si. The fabricated devices, whose NW width is 9.6 nm, exhibit nearly ideal SS of 60 mV dec−1 at room temperature. Furthermore, relatively high field effect mobility, small device-to-device SS variations and negligible temperature dependence are observed, indicating the device is promising for future three-dimensional integration.