Silicon Nanotube FET Research Articles

Negative capacitance silicon nanotube FET: a subthreshold modeling exploration of sub-60 mV/decade swing, negative drain-induced barrier lowering, and threshold voltage roll-off

Negative capacitance silicon nanotube FET: a subthreshold modeling exploration of sub-60 mV/decade swing, negative drain-induced barrier lowering, and threshold voltage roll-off

Impact of ambient temperature and thermal resistance on device performance of junctionless silicon-nanotube FET

In this article, a comprehensive analysis of the impact of electrothermal characteristics in the junctionless silicon-nanotube (Si-NT) field-effect-transistors is carried out using the Sentaurus TCAD. The combined study of the variation in thermal contact resistance (1 × 10−9 to 1 × 10−8 m2 W K−1), ambient temperature (300–400 K), and spacer length (5–20 nm) are performed. Significant improvements are observed in carrier temperature by 14%, lattice temperature by 13.7%, and gate leakage current from 0.787 nA to 0.218 fA due to the change in the spacer length. Further, a change in the drain current of 25.6% for thermal resistance (R th) and of 11.62% due to ambient temperature is observed. We also show that the junctionless device suffers significantly less from self-heating effects because of the electric field intensity, which is much lower in the channel region.

DC and RF analysis of vertical 3D p-type silicon nanotube FET for low power applications

ABSTRACT A vertical p-type 3D silicon nanotube field effect transistor (p-type Si-NTFET) is designed and simulated by using the tool Sentaurus Technology computer-aided design (TCAD). To improve the performance with reduced short channel effects, Si-NTFET device is created with inner and outer gate structures. The performance of the proposed device is analysed in terms of outer gate length. The vertical 3D p-type Si-NTFET gives an on state current (I ON) of −2.084 × 10−3 A/µm, off state current of (I OFF) of −2.457 × 10−12A/µm and subthreshold swing of the p-type Si-NTFET device is 53 mV/dec at V DS of −0.3 V. The obtained I ON/I OFF ratio of the device is 109. The capacitances (C GD, C GG) and the transconductance (g m) and cutoff frequency (f t) of the device are also analysed. The simulated p-type Si-NTFET device has proved that the device is suitable for low-power applications.

Soft error study on junctionless silicon nanotube FET based 6T SRAM cell

In this work, the response of Junctionless Silicon Nanotube FET (JL SiNT FET) to the heavy ion irradiation and the soft error performance of JL SiNT FET based SRAM circuit are investigated using 3D numerical simulations. The impact of single event transient (SET) is studied at different locations of junctionless SiNT with different incident angles to identify the sensitive location of the device. After SET analysis, JL SiNT FET based 6T SRAM cell is studied for single event upset (SEU). Heavy ion study of JL SiNT FET is compared with junction based SiNT FET. The simulation result shows that the threshold linear energy transfer (LETth) of JL SiNT FET based SRAM is approximately three times lesser than the junction based SiNT FET SRAM.

Tuning of Threshold Voltage in Silicon Nano-Tube FET Using Halo doping and its Impact on Analog/RF Performances

In this paper, a novel method is proposed for the first time to achieve multiple threshold voltage (VT) for Silicon Nanotube FET. Using TCAD simulator, it is shown that threshold voltage can be varied by tuning the halo doping and tube diameter of Silicon Nanotube FET. The typical method to attain multiple threshold voltages is to select the pertinent gate work-function for individual devices. But this is not practically feasible due to the difficult process complexity. In this work, the tuning of halo doping and nanotube diameter can be elected to provide three possible values of VT at 14-nm technology node. Furthermore, short-channel effect like Drain Induced Barrier Lowering (DIBL) is also found to be reduced with HALO doped region at source side. It is also observed that the threshold voltage decreases while increasing the tube diameter. Moreover, HALO doping at drain side is found showing a significant improvement in analog/RF performances of the device which eventually makes the device more suitable for radio-frequency integrated circuit applications.

Temperature sensitivity analysis of inner-gate engineered JL-SiNT-FET: An Analog/RF prospective

This paper explores the temperature sensitivity of Inner-gate engineered junctionless silicon nanotube FET (JL-SiNT-FET) on analog/RF performance. It is found that the reduction in the operating temperature from 400 K to 100 K improves the various analog/RF figure of merits (FOMs) of all the three configurations (DS-JL-SiNT-FET, D-JL-SiNT-FET, and S-JL-SiNT-FET) of JL-SiNT-FET by considerable expanse. The improvement in intrinsic dc gain (AV) is found to be ~1.8 dB, 2.2 dB, and 1.6 dB respectively for DS-JL-SiNT-FET, D-JL-SiNT-FET, and S-JL-SiNT-FET when the working temperature is reduced from 400 K to 100 K. Additionally, the improvement in cut-off frequency (fT), maximum oscillation frequency (fMAX), and gain-frequency product (GFP) caused by temperature variation are correspondingly significant in all the three configurations of JLSiNT-FET. It is also observed that the improvement (ΔF = FT=100 - FT=400, where F is the analog/RF FOM) caused by the reduction in temperature is almost similar in all the configurations.

Comparative analysis of silicon nano tube FET for switching applications using high K and work function modulation

In this paper we studied the impact of variation of dielectric constant and alternation of gate work function on silicon nanotube FET for low power and high speed switching applications. The silicon nano tubular structure offers better immunity towards short channel effects. Due to the gate engineered structure high K value structures possess high value of electron velocity. In this paper we have considered a silicon dioxide (SiO2), silicon nitride (Si3N4), hafnium oxide (HfO2), hafnium silicate (HfSiO4), tin oxide (SnO2) and titanium oxide (TO2) as a gate dielectric. Further by tuning the gate work function of the device we can able to achieve multiple threshold voltages and optimise the performance of the device. In this paper we discuss the impact of work function variation on ON-current, OFF-current and threshold voltage. From the analysis it has been found that HfO2 in SINTFET will be a superior alternative for future tubular FET devices and by tuning the gate work function nearby to 4.8 eV the silicon nano tube shows optimised better performance among all other values.

Investigation of Temperature and Source/Drain Overlap Impact on Negative Capacitance Silicon Nanotube FET (NC Si NTFET) with Sub-60mV/decade Switching

In this paper, the impact of temperature and source/drain overlap on DC characteristics and analog/RF performance of the negative capacitance silicon nanotube FET (NC Si NTFET) have been presented. The performance of the device is examined by coupling the 3D TCAD numerical simulation with 1D Landau-Khalatnikov (LK) equation. The effect of negative capacitance has been investigated for different source/drain overlap lengths (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ov</sub> ) at 300 K and 380 K. The optimal values of source/drain overlap lengths and effective ferroelectric thickness (t <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</sub> ) have been found to attain significant improvement in device performance in terms of drain current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> ), subthreshold swing (SS), gate capacitance (C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> ), and cut-off frequency (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> ). It is reported that a minimum SS of 30.7 mV/decade, and maximum f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> of 2.35 THz are achieved for NC Si NTFET at 300 K for an operating frequency of 1 GHz. It is observed that the core (inner gate) radius (t <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> ) can be used to increase the minimum SS and I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> to delay the hysteresis and to achieve a better drive current.

Effect of strain in silicon nanotube FET devices for low power applications

In this paper, we have presented an analysis on the performance of a strained silicon channel in silicon nanotube FET (Si-NTFET) device. Si-NTFET devices have tube-shaped channel region and because of this conduction in the channel can be controlled in two ways from outside the tube and from inside (from hollow side) the tube which results in better control over the short channel effects (SCEs). Bi-axial strain induced into the device by the inclusion of silicon-–germanium layer in between the channel. Three-dimensional simulations of the structure are carried out using ATLAS TCAD simulator and the model is calibrated with respect to previously published experimental data. The transfer characteristics, drain induced barrier lowering (DIBL), threshold voltage, Ion and Ioff, subthreshold swing of the Si-NTFET and strained Si-NTFET devices are investigated. It is seen that in strained Si-NTFET, the drive capability and inversion charge density is much higher compared to that of Si-NTFET. Evaluation of electrical performances confirms that the DIBL and other SCEs are either reduced or remains the same. However, the use of strained Si-NTFET is more suited for high speed and low power applications.

Impact of structural process variation on junctionless silicon nanotube FET

In this paper, the impact of process variation on the performance parameters of junctionless silicon nanotube field effect transistor (JLSiNT-FET) is studied using 3D numerical simulations. The performance metrics, ON current, OFF current, and unity gain frequency are taken for different physical factors. Sensitivity of the physical factors is computed over a range at various points. The ranking of the structural parameters for various performance metrics is done using a two level full factorial design of experiment method. Overall ranking proposes that the outer diameter of the silicon tube is the most sensitive parameter and inner diameter of the silicon tube is the least sensitive parameter.

Study of temperature effect on junctionless Si nanotube FET concerning analog/RF performance

This paper for the first time investigates the effect of temperature variation on analog/RF performance of SiO2 as well as high-K gate dielectric based junctionless silicon nanotube FET (JL-SiNTFET). It is observed that the change in temperature does not variate the analog/RF performance of junctionless silicon nanotube FET by substantial amount. By increasing the temperature from 77 K to 400 K, the deterioration in intrinsic dc gain (AV) is marginal that is only ∼3 dB. Furthermore, the variation in cut-off frequency (fT), maximum oscillation frequency (fMAX), and gain-frequency product (GFP) with temperature is also minimal in JLSiNT-FET. More so, the same trend is observed even at scaled gate length (Lg = 15 nm). Furthermore, we have observed that the use of high-K gate dielectric deteriorates the analog/RF performance of JLSiNT-FET. However, the use of high-K gate dielectric negligibly changes the effect of temperature variation on analog/RF performance of JLSINT-FET device.

Study of 6T SRAM cell using High-K gate dielectric based junctionless silicon nanotube FET

This paper investigates the performance of 6 T SRAM cell using high-K gate dielectric based junctionless silicon nanotube FET (JLSiNTFET). It is observed that the use of high-K gate dielectric enhances the delay performance of the JLSiNTFET based 6 T SRAM cell. Read access time (RAT) and write access time (WAT) improves by ∼18% and ∼20% when TiO2 is used as gate dielectric instead of SiO2. The hold, read, and write SNMs (static noise margin) of the 6 T SRAM cell also improves marginally by the use of high-K gate dielectric. Furthermore, it is also observed that the improvement in hold SNM (HSNM), read SNM (RSNM), and write SNM (WSNM) can be boosted by using higher interfacial layer thickness (TI). However, the improvement in read access times (RAT) & write access time (WAT) degrades at higher TI. Thus, high-K gate dielectrics with high interfacial layer thickness are more suitable for JLSiNT-FET based 6 T SRAM cell.

Effect of eccentricity on junction and junctionless based silicon nanowire and silicon nanotube FETs

In this paper, the effect of eccentricity on Junction-based Silicon Nanowire FET, Junction-based Silicon Nanotube FET, Junctionless-based Silicon Nanowire FET, and Junctionless-based Silicon Nanotube FET is investigated. Three kinds of eccentric structures are considered here. The impact of eccentricity on effective gate oxide thickness thereby gate oxide capacitance, and effective channel width are studied using 3D numerical simulations. Average radius of an ellipse is used to generate a model which captures the impact of eccentricity on gate oxide capacitance, and verified using TCAD simulations in MOS nanowire structure. The impact of eccentricity on ON current (ION), OFF current (IOFF), ION/IOFF ratio, and Unity gain cutoff frequency are investigated. Eccentricity increases the effective gate oxide thickness, the effective channel width, ION, and IOFF but reduces ION/IOFF ratio.

Silicon nanotube SRAM and its SEU reliability

In this work, silicon nanotube FET (SiNT FET) based 6T SRAM cell operation is demonstrated and its Read, Write and Hold SNMs (static noise margin) are analyzed. The SRAM is also investigated for one of the important dynamic stability performance metrics, single event upset under heavy ion irradiation (SEU). Three different striking locations (region closer to source, center of channel and region closer to drain) and three different striking angles are used during SEU study. The worst case threshold Linear Energy Transfer (LET) is found to be 36 MeV/(mg/cm2). All the studies are carried out using mixed mode 3D numerical simulations.