Study of 6T SRAM cell using High-K gate dielectric based junctionless silicon nanotube FET

Abstract

This paper investigates the performance of 6 T SRAM cell using high-K gate dielectric based junctionless silicon nanotube FET (JLSiNTFET). It is observed that the use of high-K gate dielectric enhances the delay performance of the JLSiNTFET based 6 T SRAM cell. Read access time (RAT) and write access time (WAT) improves by ∼18% and ∼20% when TiO2 is used as gate dielectric instead of SiO2. The hold, read, and write SNMs (static noise margin) of the 6 T SRAM cell also improves marginally by the use of high-K gate dielectric. Furthermore, it is also observed that the improvement in hold SNM (HSNM), read SNM (RSNM), and write SNM (WSNM) can be boosted by using higher interfacial layer thickness (TI). However, the improvement in read access times (RAT) & write access time (WAT) degrades at higher TI. Thus, high-K gate dielectrics with high interfacial layer thickness are more suitable for JLSiNT-FET based 6 T SRAM cell.