Abstract
This article presents a new way for designing a more reliable and variability resilient 9T SRAM cell which is based on DTMOS (dynamic threshold MOS) and CCBB (cell content body bias) technique under subthreshold operation. Critical design metrics of SRAM cells are estimated at subthreshold region and compared with that of conventional 9T SRAM cell. The proposed 9T SRAM cell shows 41.8% (9.5%) lower read access time (write access time) compared to conventional 9T SRAM cell. It also exhibits robustness by achieving narrower spread in read access time (write access time) by 53.01% (8%) compared to its conventional 9T SRAM cell. Moreover, the proposed bitcell offers 9.5% (47.4%) improvement in read static noise margin (write static noise margin) @ 350 mV.
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