Comparative study of CMOS- and FinFET-based 10T SRAM cell in subthreshold regime

Abstract

This article presents a variability resilient FinFET based 10T SRAM cell. Critical design metrics of SRAM cells are estimated at subthreshold region and compared with that of conventional MOSFET based 10T SRAM cell. The FinFET based SRAM cell offers 2.33× and 1.29× improvements in Read Access Time (T RA ) and Write Access Time (T WA ) respectively. The proposed bitcell also offers 7.06× and 1.54× improvements in T RA and T WA variability respectively compared to its MOSFET counterpart. Moreover, our bitcell exhibits 20% higher read static noise margin (RSNM) at a cost of 5% reduction in write static noise margin @ 400 mV.