Silicon Interposer Research Articles

Reliability Simulation Analysis of TSV Structure in Silicon Interposer under Temperature Cycling.

As semiconductor integration scales expand and chip sizes shrink, Through Silicon Via (TSV) technology advances towards smaller diameters and higher aspect ratios, posing significant challenges in thermo-mechanical reliability, particularly within interposer substrates where mismatched coefficients of thermal expansion exacerbate issues. This study conducts a thermo-mechanical analysis of TSV structures within multi-layered complex interposers, and analyzes the thermal stress behavior and reliability under variable temperature conditions (-55 °C to 85 °C), taking into account the typical electroplating defects within the copper pillars in TSVs. Initially, an overall model is established to determine the critical TSV locations. Sub-model analysis is then employed to investigate the stress and deformation of the most critical TSV, enabling the calculation of the temperature cycle life accordingly. Results indicate that the most critical TSV resides centrally within the model, exhibiting the highest equivalent stress. During the temperature cycling process, the maximum deformation experiences approximately periodic variations, while the maximum equivalent stress undergoes continuous accumulation and gradually diminishes. Its peak occurs at the contact interface corner between the TSV and Redistribution Layer (RDL). The estimated life of the critical point is 3.1708 × 105 cycles. Furthermore, it is observed that electroplating defect b alleviates thermal stress within TSVs during temperature cycling. This study provides insights into TSV thermal behavior and reliability, which are crucial for optimizing the design and manufacturing processes of advanced semiconductor packaging.

An ultra-deep TSV technique enabled by the dual catalysis-based electroless plating of combined barrier and seed layers

Silicon interposers embedded with ultra-deep through-silicon vias (TSVs) are in great demand for the heterogeneous integration and packaging of opto-electronic chiplets and microelectromechanical systems (MEMS) devices. Considering the cost-effective and reliable manufacturing of ultra-deep TSVs, the formation of continuous barrier and seed layers remains a crucial challenge to solve. Herein, we present a novel dual catalysis-based electroless plating (ELP) technique by tailoring polyimide (PI) liner surfaces to fabricate dense combined Ni barrier/seed layers in ultra-deep TSVs. In additional to the conventional acid catalysis procedure, a prior catalytic step in an alkaline environment is proposed to hydrolyze the PI surface into a polyamide acid (PAA) interfacial layer, resulting in additional catalysts and the formation of a dense Ni layer that can function as both a barrier layer and a seed layer, particularly at the bottom of the deep TSV. TSVs with depths larger than 500 μm and no voids are successfully fabricated in this study. The fabrication process involves low costs and temperatures. For a fabricated 530-μm-deep TSV with a diameter of 70 μm, the measured depletion capacitance and leakage current are approximately 1.3 pF and 1.7 pA at 20 V, respectively, indicating good electrical properties. The proposed fabrication strategy can provide a cost-effective and feasible solution to the challenge of manufacturing ultra-deep TSVs for modern 3D heterogeneous integration and packaging applications.

Technology for Manufacturing TSV Structures for the Creation of Silicon Interposers Using Temporary-Bonding Technology

Technology for Manufacturing TSV Structures for the Creation of Silicon Interposers Using Temporary-Bonding Technology

Modeling and signal integrity analysis of silicon interposer channels based on MTL and KBNN

In this paper, the equivalent circuit model of interconnect channels in silicon interposer is developed for three-dimensional integrated circuit (3-D IC) based on the theory of multi-conductor transmission line (MTL). The deep neural network (DNN) is employed to learn the nonlinear mapping relationship between the geometric parameters and the distributed parameters, and it is demonstrated that the DNN has a high prediction accuracy. In the implementation, a coarse model is firstly developed by solving the scattering parameters of the model using the chain parameter matrix. The model is optimized using a knowledge-based neural network (KBNN), and a fine model is then established. The numerical examples demonstrate that the optimized model can achieve high accuracy. Finally, the inner contour of the worst-case eye diagrams of the channel is generated using the peak distortion algorithm (PDA), with the worst eye width and height obtained.

An efficient Green's function-based Bayesian optimization method for the thermal optimization of multi-chips on a silicon interposer

The escalating adoption of multi-chips configurations in integrated circuits has intensified concerns about power density and heat generation. Inadequate chip layout design can lead to localized overheating, triggering chip component degradation and a decline in module performance. Consequently, proficient thermal design and temperature regulation are crucial. This paper presents a rapid optimization methodology that merges Green's function (GF) and Bayesian optimization (BO) to improve the thermal placement optimization of multiple chips on a silicon interposer. An efficient GF method is proposed as a replacement for the time-consuming finite element method (FEM), offering an exhaustive thermal analysis for the entire model. The accuracy of this method is validated through a comparative analysis with FEM, revealing a maximum deviation of less than 0.6% in the steady-state temperature field of the multi-chips model with various chip numbers and chip powers. Notably, GF exhibits a markedly superior computational speed compared to FEM. The GF requires only 0.4 s for a single temperature distribution calculation, making it 60 times faster than the FEM. Subsequently, the analytical solution is combined with the BO algorithm, and its performance is evaluated. The results indicate that, compared to five other optimization algorithms, the BO algorithm can most rapidly find the most ideal optimization layout. The calculation speed of the BO algorithm is 4.5 times faster than the Particle Swarm Optimization algorithm and 4 times faster than the Surrogate Optimization algorithm. The efficiency and accuracy of the proposed GF-based BO approach demonstrates considerable potential in expediting the thermal placement optimization for multi-chips configurations.

An Analysis of Various Design Pathways Towards Multi-Terabit Photonic On-Interposer Interconnects

In the wake of dwindling Moore’s Law, to address the rapidly increasing complexity and cost of fabricating large-scale, monolithic systems-on-chip (SoCs), the industry has adopted dis-aggregation as a solution, wherein a large monolithic SoC is partitioned into multiple smaller chiplets that are then assembled into a large system-in-package (SiP) using advanced packaging substrates such as silicon interposer. For such interposer-based SiPs, there is a push to realize on-interposer inter-chiplet communication bandwidth of multi-Tb/s and end-to-end communication latency of no more than 10 ns. This push comes as the natural progression from some recent prior works on SiP design, and is driven by the proliferating bandwidth demand of modern data-intensive workloads. To meet this bandwidth and latency goal, prior works have focused on a potential solution of using the silicon photonic interposer (SiPhI) for integrating and interconnecting a large number of chiplets into an SiP. Despite the early promise, the existing designs of on-SiPhI interconnects still have to evolve by leaps and bounds to meet the goal of multi-Tb/s bandwidth. However, the possible design pathways, upon which such an evolution can be achieved, have not been explored in any prior works yet. In this paper, we have identified several design pathways that can help evolve on-SiPhI interconnects to achieve multi-Tb/s aggregate bandwidth. We perform an extensive link-level and system-level analysis in which we explore these design pathways in isolation and in different combinations of each other. From our link-level analysis, we have observed that the design pathways that simultaneously enhance the spectral range and optical power budget available for wavelength multiplexing can render aggregate bandwidth of up to 4 Tb/s per on-SiPhI link. We also show that such high-bandwidth on-SiPhI links can substantially improve the performance and energy-efficiency of the state-of-the-art CPU and GPU chiplets based SiPs.

Optimized Signal and Power Integrity of Silicon Interposer for HBM2E in CoWoS Packaging

Optimized Signal and Power Integrity of Silicon Interposer for HBM2E in CoWoS Packaging

(Invited, Digital Presentation) Overview of Current and Future 3D Heterogeneous Integration Architectures

High performance computing architectures such as high core count servers and AI accelerators have increasing demands on performance and energy efficiency. This requires power efficient and high bandwidth integration of multiple functions such as processing, memory and high speed circuits in a single package. Current trend is to separate these functions into chiplets with optimized technology then integrating them using advanced packaging technologies that target ease of integration, low overhead and maximum flexibility. In this talk, we will provide an overview of current and future 3D packaging technologies. We will start with solder silicon interposers which enable die stacking to support improved logic density/mm2 of package area and cover their design considerations and applications. Next, we will cover local silicon interconnect architectures which bridge the flexibility gap between 2.5D architectures and 3D interposer architectures. Afterwards, we will discuss the next generation architectures which are based on hybrid bonding. These architectures offer much higher interconnect density up to >100,000 connections/mm2 and enable new types of integration. Finally, we will discuss some future directions to continue to support performance and bandwidth scaling.

The Evolution of Moore’s Law Through Chipletized Architectures

Staying ahead of America’s adversaries requires control of the electromagnetic spectrum and therefore an evolution of the sensor processing chain. Agile, chip-scale, direct analog-to-digital solutions at the sensor edge are needed to overcome data bandwidth and latency limitations that are inherent with legacy EW and radar systems, and reduce design cycles, size, weight, power, and cost (SWaP-C). Heterogeneous, 2.5D integration is the next phase of Moore’s Law enabling a new approach to microelectronics based on chipletized architectures. The acceleration of deployable modular, high-performance microelectronics to the tactical edge is achieved by integrating the best silicon processing nodes for analog/digitization, processing, memory, and AI functionality on one chip. Mercury is partnering with leading semiconductor providers to deliver to defense customers the only trusted, RF system-in-package (RFSiP) devices that utilize an ecosystem of advanced, die-level building blocks, called chiplets, at the speed of innovation and purpose-built for each mission. Through assembly of high-density chiplets on a silicon interposer, on-chip die-to-die interconnects enable efficient conversion between analog and digital signals, signal processing, high-speed IO, and power management while reducing system complexity and SWaP-C. The use of open standard die-to-die interfaces allows chiplets to be rapidly upgraded or modified to meet the intended use case. In this paper, Mercury explores how 2.5D integration of state-of-the-art chiplets on a silicon interposer solves next-generation EW and radar system data processing challenges.

Analytical equivalent circuit modeling and analysis of complex BGA for 3D silicon-interposer packaging

Through analyzing different cross-sections of the complex ball grid array (CBGA) sandwiched by silicon interposers, various distributed capacitances of the CBGA and the significance of the CBGA's coplanar capacitances are revealed. From the analyses, the composition of the CBGA's capacitance is found to have similarity with that of the coplanar waveguide's capacitance. Based on the electric-field coupling mechanism of the coplanar waveguide, geometrical analysis of the CBGA, and analysis of multiconductor transmission lines, analytical equations are derived to allow accurate modeling the equivalent circuit of the CBGA for 3D silicon-interposer packaging. The modeled equivalent circuit of the CBGA is validated with the full wave electromagnetic simulation, and it is demonstrated to have a good accuracy up to 40 GHz. Moreover, the CBGA structure can be further optimized for impedance matching with the guidance of the derived analytical equations.

Advanced Test Technologies for Heterogeneous & 2.5D/3D Packaging

Automotive, AI/ML and 5G markets are demanding increasing levels of integration with respect to memory and compute density. To meet the demand for high-performance products in mission-critical, high-bandwidth applications, the semiconductor industry must look for innovative technologies to continue scaling beyond the silicon manufacturing processes. This is often referred to as “More than Moore”, and one of the most promising methods is heterogenous integration of multiple dies inside the same package (System in Package, or SiP). These dies are typically referred to as chiplets and their interfaces are optimized to operate within a multi-die package for both power, drive strength, interface mechanics and ESD protection. Heterogeneous packages at manufacturing test are faced with quality and reliability challenges due to the accessibility and visibility of traditional test approaches. Dies are assembled over the silicon interposer using very small micro-bumps which may suffer from latent defects such as voids or cracks, potentially posing a reliability risk to the assembled product. On organic substrates, rare resistive shorts, known as bridging shorts, can cause signal integrity and performance degradation. These types of latent defects, although rare, could cause a system failure over time if not screened out during final test or detected during in-field operation. To address these challenges, proteanTecs and Advantest have deployed a joint solution at manufacturing test. proteanTecs provides a monitoring solution for heterogeneous packaging based on chip telemetry, combining deep data with machine learning algorithms. proteanTecs’ patent-protected solution is comprised of small-footprint, digital-only agents for monitoring the performance of the parallel interface. These agents (monitoring IP) are designed for analytics. The fact that they have a small footprint, allows them to be placed next to each pin inside the parallel die-to-die (D2D) PHY, to achieve 100% coverage and with no impact on the signal behavior, quality, or timing. proteanTecs’ data analytics platform then trains models that are deployed at test or in the field. To achieve the highest levels of performance, proteanTecs has partnered with Advantest on the ACS Edge™ for real-time decision-making. ACS Edge™ is a high-performance, highly secure edge compute and analytics solution that enables ultra-fast algorithmic AI decision-making with millisecond latencies during test execution. It connects to the user’s test equipment via a private, high-speed encrypted link and uses the advanced container hub to run the user’s protected applications while protecting and keeping secure the user’s data and analytics. Another key piece of the ACS ecosystem is the ACS Solution Store which provides ease of access to ACS real-time data infrastructure solutions. In this paper, we will provide details for the integrated solution and silicon results. We will highlight how the solution provides new levels of visibility for real-time adaptive testing.

Designing Silicon Interposers for 2.5/3DIC Heterogeneous Integration - Meeting Foundry and OSAT Requirements

End market demand for higher performance, higher bandwidth and higher throughput processing such as AI, HPC, VR, 5G and even autonomous vehicles is driving the trend of heterogenous integration of ASICs, chiplets and memory, including HBM, onto advanced high-performance substrates using 2.5 and 3D IC assembly techniques that are manufactured using silicon or silicon-like processes. There are multiple suppliers of such advanced high-performance substrates ranging from the one stop mega foundries to multiple OSATs of different sizes. It’s fair to say that all of them have common design requirements or constraints that must pass a rigorous verification process of the manufacturing mask files (GDSII or OASIS). Such GDSII or OASIS files are post processed or exported from the physical design tools making the need to create the mask files with 100% fidelity an additional challenge to the design team. In this paper we will cover the major steps needed to design and implement an advanced silicon-based interposer that addresses common requirements of foundries and OSATs. We will talk about what each step is, why its required, any challenges that exist in addressing the step and actual design examples for each step. The major steps we will cover include: * What information you need from your manufacturer? * Definition of connectivity & floorplanning of the interposer * Defining the interposer materials stackup & vias for routing * Breakout or fanout routing from chiplet or IC pads * Power and ground mesh creation * Routing of interposer connectivity * Generation of interposer manufacturing data (GDS/OASIS) * Verification of the design to meet foundry/OSATs rules * Handoff to foundry/OSAT At the end of this paper attendees will understand what the major workflow steps for interposer design are and why. What general information they will need to obtain from their manufacturer in order to start design and how to use it. They will learn what each design step entails with clear examples which will enable creation of workflows to successfully handoff their designs to their chosen foundry or OSAT manufacturer.

Electrical Performance Analysis of High-Speed Interconnection and Power Delivery Network (PDN) in Low-Loss Glass Substrate-Based Interposers.

In this article, electrical performance analysis of high-speed interconnection and power delivery network (PDN) in low-loss glass substrate-based interposers is conducted considering signal integrity (SI) and power integrity (PI). The low-loss glass substrate is a superior alternative to silicon substrate in terms of high-speed signaling and fabrication yield. However, the low-loss of the substrate is vulnerable to power/ground noise in the PDN since the low-loss property of the substrate cannot suppress the noise naturally. In this article, an in-depth electrical performance analysis is conducted based on various measurements and simulations to fully benefit the advantages of the low-loss glass substrate. First, the fabrication process and test vehicles for the analysis are explained. Using the test vehicles, the electrical performance of the glass interposer's high-speed interconnection is compared with those of silicon and organic interposers. The insertion loss, eye-diagrams, and signal bandwidths of three interposer channels are compared and analyzed based on electromagnetic (EM) and circuit simulations. Also, the electrical performance of the through glass via (TGV) channel is measured and compared with through silicon via (TSV) channel. The high-speed interconnection of the glass interposer showed better performance for most of the parameters which is more suitable for maintaining the SI. Even though the low-loss of the glass substrate ensured the SI, power/ground noise issues in the PDN must be analyzed and solved. In this article, various cases inducing the power/ground noise in the PDN are considered, simulated, and measured. To solve the issues, ground TGV design and electromagnetic bandgap (EBG) design are proposed for an efficient broadband suppression of the noise generated in the glass interposer PDN.

Multimode Optical Interconnects on Silicon Interposer Enable Confidential Hardware-to-Hardware Communication.

Following Moore's law, the density of integrated circuits is increasing in all dimensions, for instance, in 3D stacked chip networks. Amongst other electro-optic solutions, multimode optical interconnects on a silicon interposer promise to enable high throughput for modern hardware platforms in a restricted space. Such integrated architectures require confidential communication between multiple chips as a key factor for high-performance infrastructures in the 5G era and beyond. Physical layer security is an approach providing information theoretic security among network participants, exploiting the uniqueness of the data channel. We experimentally project orthogonal and non-orthogonal symbols through 380 μm long multimode on-chip interconnects by wavefront shaping. These interconnects are investigated for their uniqueness by repeating these experiments across multiple channels and samples. We show that the detected speckle patterns resulting from modal crosstalk can be recognized by training a deep neural network, which is used to transform these patterns into a corresponding readable output. The results showcase the feasibility of applying physical layer security to multimode interconnects on silicon interposers for confidential optical 3D chip networks.

A novel chip-scale heterogeneous integration intelligent micro-system of short wave infrared imaging

In this paper, a novel heterogeneous integrated intelligent micro sensing system for short-wave infrared (SWIR) sensing and processing is proposed, which can detect and recognize objects based on image signals, and realize the complete function of “sensing-process-communication” at the chip scale. Here, we innovatively adopt chip scale heterogeneous integration (CSHI) to achieve high-density integration of sensor, analog and digital chips with different substrates and different process nodes by vertically interconnecting the 2.5 dimension (2.5 D) Through-Silicon Via (TSV) silicon interposer and 3 dimension (3D) high temperature co-fired ceramics (HTCC) ceramics. The short-wave infrared image detection and recognition system with high performance, small size and high reliability is realized on the premise of maintaining good interconnect power supply and signal integrity, and the feasibility of the proposed comprehensive approach is verified. Sensors, analog and digital chips of different substrates and process nodes are integrated into a micro-system at the chip level through this approach. The approach presented in this paper is an effective solution to realize intelligent sensing micro-system, which can effectively extend functions and improve integration level at the chip scale.

Microfluidic silicon interposer for thermal management of GaN device integration

With the popularity of the third generation semiconductor applications, silicon-based hetero-integration is driven to be applied massively by the miniaturization of microsystems and modules. The system-level power has a sharp increase in recent years, and consequently, hotspot thermal management is being increasingly concerned. A high-power GaN device with chip heat fluxes > 500 W/cm2 and hotspot heat fluxes > 30 kW/cm2 is implemented in this work to study extremely uneven hotspot cooling for silicon-based hetero-integration. A customized microjet silicon interposer (SI) is designed and fabricated based on the on-chip hotspot distribution, and another common microchannel SI in similar sizes is prepared for comparison. The GaN device is integrated on SI and micro-assembled in a test cube. The measurement results demonstrate that the maximum junction temperature of the GaN device on microjet SI is down to 150.3 ℃ at 70 ℃ ambient temperature with a pressure drop of 231.9 kPa. The overall thermal resistance (TR) of the test vehicle with microjet cooling has a 7.11 ∼ 7.72 % reduction and its heat transfer coefficient (HTC) increases by 12.3 ∼ 28.3 % compared to that with microchannel cooling with the pumping power of 0.5 ∼ 1.5 W. The material properties of the GaN chip and SI are extracted from the measurement results and then used in the analysis of the thermal and hydraulic properties of both microfluidic SIs numerically. Their cooling performance and efficiency are evaluated and compared based on the performance evaluation criteria (PEC), field synergy number and entropy generation rate. According to the evaluation results, while the PEC of microjet and microchannel SIs increases with the pumping power, the microjet SI can contribute to the enhancement of the synergetic relationship between the flow and temperature fields and reduction of total irreversibility in the heat transfer process compared to the microchannel SI in pursuit of low overall TR. The field synergy number improves by 90.40 % and the argument entropy generation rate is 0.376 when the overall TR is 1.35 K/W. The findings can provide valuable references for hotspot thermal management in silicon-based hetero-integration.

Assembly Technology for FO-MCM with HBM in HPC Application

As the industry moves forward the age of more than Moore, the next generation of packaging moves forward high density of chiplet or die splitting package integration. Especially for high performance computing applications, the advance packaging is to provide the economic benefits to integrate multiple chiplet dies by silicon or organic interposer. Organic interposer is one of the alternative interface for die to die interconnection. It is well-known by FO-MCM to apply in chiplets integration and ASIC to Serdes dies integration by the homogeneous package integration concept. Due to the motivation of AI computing and HPC market growth, the trend is formed to integrate the packaged HBM into packaging module as the heterogeneous integration package (HIP). Both of the platforms, 2.5D with silicon interposer base and FO-EB with partial bridge die as interconnection media, have already launched to market in recent years. FO-MCM with purely organic interposer, is also discussed to implement into the heterogeneous integration field. The fully organic interposer can provide the flexible design in multiple RDL layers and line / space for HPC products. In this study, it is to address FO-MCM platform with purely organic interposer to implement heterogeneous packaging with integrated HBMs. Chip last approach in FO-MCM has the advantage to control RDL quality and take “known-good RDL” for top die cost rescuing. The fan-out RDL configuration is 4 layers with min, L/S of 2/2um. In the verification processes, based on the simulation analysis, the warpage and stress are optimized by material and under-fill selections in this discussion. The assembly results indicated the warpage and reliability validation passed by MSL4, TCT700x, uHAST96, and HTST1000hrs conditions.

An Organic Package Designer’s Guide to Transitioning to FOWLP and 2.5D Design

Many package designers have many years of hands-on experience designing organic FR4/HDI build-up BGA/LGA substrates. We’ve memorized the design guidelines and the substrate fabrication is well understood. We know how to wield our design tools like precision scalpels to get the design completed on-time, on-specification and on budget. Whether it’s flipchip attach, wire bond or a stacked die combo the design methodology is well understood. Then management mentions that the next generation of designs are going to be “heterogeneously integrated”, utilizing new integration platforms such as RDL-based fan-out wafer level and/or interposers. Suddenly, people start mentioning things like “Assembly Design Kits”, “Stream-out”, “sign-off using PDK’s”, multi-pass degassing, seal rings, assembly LVS and HBM stack routing. The suggestion is made that new design tools might be needed – semiconductor P&R tools that only work on Linux and are all TCL/TK script driven. We start doing some research online and attend a conference or two and listen to some of the EDA tool vendors and you could easily arrive at a point where you start to think, “Am I obsolete? Do I really need to learn to use silicon P&R tools? What is “assembly LVS”, multiple-pass degassing and why do my metal planes need to be hatched and offset?” For many of us, the shift in technology can be overwhelming. Do not despair; yes, there is new terminology to understand and many new design techniques to be understood and mastered, as well as a completely new design process and flow. The good news is that this can all be overcome without having to learn silicon P&R design tools. This paper will discuss real-world experiences of organic package substrate designers who have transitioned and mastered RDL-based FOWLP and 2.5D silicon and organic interposer design, while still using (and preserving) the majority of their existing packaged design tools and skills.

A 0.297-pJ/Bit 50.4-Gb/s/Wire Inverter-Based Short-Reach Simultaneous Bi-Directional Transceiver for Die-to-Die Interface in 5-nm CMOS

This article presents a clock-forwarded, inverter-based short-reach simultaneous bi-directional (ISR-SBD) physical layer (PHY) targeted for die-to-die communication over silicon interposers or similar high-density interconnect. Short-reach links of this type are increasingly important to support larger systems built with chiplets and multiple die and to facilitate the shift to medium- and long-range optical communication based on silicon photonics. This project explores the advantages of simultaneous bi-directional signaling (SBD) over other bandwidth-doubling techniques (e.g., PAM4). Fabricated in a 5-nm standard CMOS process, the ISR-SBD PHY demonstrates 50.4 Gb/s/wire (25.2 Gb/s each direction) and 0.297 pJ/bit on a 750-mV supply over a 1.2-mm on- chip channel.

Beyond CPO: A Motivation and Approach for Bringing Optics Onto the Silicon Interposer

Co-packaged optics (CPO) technology is well positioned to break through the bottlenecks that impede efficient bandwidth scaling in key near-term commercial integrated circuits. We begin by providing some historical context for this important sea change in the optical communications industry. Then, motivated by GPU-based accelerated computing requirements, we investigate the next pain points that are poised to constrain bandwidth and efficiency in future CPO-based systems. We identify 2.5D integrated optics (i.e., bringing optics onto the interposer) as a promising solution that can enable continued scaling for these systems due to the dense wiring available which facilitates more efficient slow-and-wide electrical interfaces. We explore the benefits, challenges, and requirements associated with such tight coupling of the processors and optical engines by considering high-level photonic link design, technology, and packaging. We demonstrate the viability of a control loop which can adequately regulate temperature within the aggressive thermal environment. Then, we introduce a custom simulation framework that allows quantified comparisons of detailed design decisions; the simulations validate the feasibility of the general approach while also providing key guidance to designers on best directions to pursue for efficient optimization.