The Evolution of Moore’s Law Through Chipletized Architectures

Abstract

Staying ahead of America’s adversaries requires control of the electromagnetic spectrum and therefore an evolution of the sensor processing chain. Agile, chip-scale, direct analog-to-digital solutions at the sensor edge are needed to overcome data bandwidth and latency limitations that are inherent with legacy EW and radar systems, and reduce design cycles, size, weight, power, and cost (SWaP-C). Heterogeneous, 2.5D integration is the next phase of Moore’s Law enabling a new approach to microelectronics based on chipletized architectures. The acceleration of deployable modular, high-performance microelectronics to the tactical edge is achieved by integrating the best silicon processing nodes for analog/digitization, processing, memory, and AI functionality on one chip. Mercury is partnering with leading semiconductor providers to deliver to defense customers the only trusted, RF system-in-package (RFSiP) devices that utilize an ecosystem of advanced, die-level building blocks, called chiplets, at the speed of innovation and purpose-built for each mission. Through assembly of high-density chiplets on a silicon interposer, on-chip die-to-die interconnects enable efficient conversion between analog and digital signals, signal processing, high-speed IO, and power management while reducing system complexity and SWaP-C. The use of open standard die-to-die interfaces allows chiplets to be rapidly upgraded or modified to meet the intended use case. In this paper, Mercury explores how 2.5D integration of state-of-the-art chiplets on a silicon interposer solves next-generation EW and radar system data processing challenges.