Abstract
Due to the increasing complexity in the power management logic of low-power designs, formal validation of the architectural power intent, comprising of both digital and analog power management features, is becoming a crucial task. Consequently, the formal verification frontier has also been extended, in recent times, to ensure the correctness for analog as well as digital power intent. The quality of verification can be evaluated by formal coverage analysis which can be determined from the reachability of safe global power states by the power manager. This article proposes a novel formal method for computing the coverage of architectural power states for power management logic having analog components like LDOs and PLLs. The efficacy of the proposed method has been shown using an industry level case-study.
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