(Invited, Digital Presentation) Overview of Current and Future 3D Heterogeneous Integration Architectures

Abstract

High performance computing architectures such as high core count servers and AI accelerators have increasing demands on performance and energy efficiency. This requires power efficient and high bandwidth integration of multiple functions such as processing, memory and high speed circuits in a single package. Current trend is to separate these functions into chiplets with optimized technology then integrating them using advanced packaging technologies that target ease of integration, low overhead and maximum flexibility. In this talk, we will provide an overview of current and future 3D packaging technologies. We will start with solder silicon interposers which enable die stacking to support improved logic density/mm2 of package area and cover their design considerations and applications. Next, we will cover local silicon interconnect architectures which bridge the flexibility gap between 2.5D architectures and 3D interposer architectures. Afterwards, we will discuss the next generation architectures which are based on hybrid bonding. These architectures offer much higher interconnect density up to >100,000 connections/mm2 and enable new types of integration. Finally, we will discuss some future directions to continue to support performance and bandwidth scaling.