Silicon Carbide Wafers Research Articles

Using Visible Laser-Based Raman Spectroscopy to Identify the Surface Polarity of Silicon Carbide

In this study we developed an approach to identify the surface polarity of silicon carbide (SiC) by using an excitation laser possessing a photon energy (2.33 eV) much lower than the band gap of 4H-SiC (3.30 eV). By gradually attenuating the intensity of the excitation laser, the effective depth that the laser could generate Raman signals could eventually be limited to within the ultrashallow region of the SiC wafer. Through three-dimensional finite-difference-time-domain (3D-FDTD) simulations, we found that the depth of the high electric field region could be limited from several micrometers below the surface to the near-surface region of 4H-SiC, merely by attenuating the power of the incident laser. Experimentally, we observed a clear trend in the Raman peak intensity ratio of the signals at 210 and 203 cm–1 in the FTA mode: the intensity ratio of the Si face was always higher than that of the C face regardless of the measurement position on the 4H-SiC wafer. Even through the carrier concentrations in the 4H-SiC wafer were nonuniform, the resulting variability in peak intensity did not influence the trend in the intensity ratio, which could, therefore, be used to identify the surface polarity. This approach might also allow characterization of different polytypes of SiC, for example, 6H-SiC and 3C-SiC, the optical band gaps of which are lower than that of 4H-SiC. Because this optical approach using low-photon-energy laser-based Raman spectroscopy is nondestructive, simple, and rapid and employs excitation light of low photon energy, it should be very applicable for characterizing the surface properties of various other crystalline materials.

Identifying Performance Limiting Defects in Silicon Carbide pn-Junctions: A Theoretical Study

Dopant implantation is a high energy process which causes a significant damage to the crystal lattice and is usually accompanied by a post implantation anneal to repair the structure. Defects created in these processes may also persist in fully processed devices. Previous electron paramagnetic resonance (EPR) and EDMR studies have identified a series of nitrogen related defect complexes in N implanted silicon carbide (SiC) wafers.[1–3] This study examines the formation energy, charge transition levels and barriers to interconversion of two such defects: NCVSi and the NSiVC. The NCVSi center is favoured in a variety of charge states for a wide range of Fermi level positions. We found, however, that for Fermi level positions close to the valence band of 4H-SiC the NCVSi center is a favoured conformation with barriers to rearrangement of +1.2 eV and +3.8 eV in the neutral and +2 charge states, respectively.

Investigation of Polishing Pads Impregnated with Fe and Al2O3 Particles for Single-Crystal Silicon Carbide Wafers

This study focuses on the development of a novel polishing pad for SiC wafers. Fe and Al2O3 particles were impregnated in a polyurethane matrix, thus forming a fixed abrasive polishing pad. Four types of pads with different compositions of Fe and Al2O3 were fabricated. A combination of loose and fixed polishing methods was used for polishing with the fabricated pads and was investigated to improve the polishing process. The surface characteristics of the polished SiC wafer and the SiC removal rate during polishing using the designed pads were examined and compared with those for SiC polished with a conventional polyurethane pad. Experimental results showed that the removal rate for SiC in the case of polishing with the pads consisting 1 wt % Fe and 3 wt % Al2O3 particles was approximately 73% higher than that observed when polishing using the conventional polyurethane polishing pad. Additionally, the surface roughness of the resulting SiC wafers after polishing with the Fe and Al2O3-impregnated pads was identical to that when using the conventional polyurethane pad, without any surface damage. The results indicated that the Fe and Al2O3-impregnated pads can be effectively used for SiC wafer polishing. When the proposed process was employed for polishing single-crystal SiC, both the polishing time and cost were reduced. This novel design can facilitate the extensive use of single-crystal SiC wafers in the future.

Surface conductance of graphene from non-contact resonant cavity

A method is established to reliably determine surface conductance of single-layer or multi-layer atomically thin nano-carbon graphene structures. The measurements are made in an air filled standard R100 rectangular waveguide configuration at one of the resonant frequency modes, typically at TE103 mode of 7.4543GHz. Surface conductance measurement involves monitoring a change in the quality factor of the cavity as the specimen is progressively inserted into the cavity in quantitative correlation with the specimen surface area. The specimen consists of a nano-carbon-layer supported on a low loss dielectric substrate. The thickness of the conducting nano-carbon layer does not need to be explicitly known, but it is assumed that the lateral dimension is uniform over the specimen area. The non-contact surface conductance measurements are illustrated for a typical graphene grown by chemical vapor deposition process, and for a high quality monolayer epitaxial graphene grown on silicon carbide wafers for which we performed non-gated quantum Hall resistance measurements. The sequence of quantized transverse Hall resistance at the Landau filling factors ν=±6 and ±2, and the absence of the Hall plateau at ν=4 indicate that the epitaxially grown graphene is a high quality mono-layer. The resonant microwave cavity measurement is sensitive to the surface and bulk conductivity, and since no additional processing is required, it preserves the integrity of the conductive graphene layer. It allows characterization with high speed, precision and efficiency, compared to transport measurements where sample contacts must be defined and applied in multiple processing steps.

Comparison on foil EDM characteristics of single crystal SiC between in deionized water and in EDM oil

Slicing of single crystal silicon carbide (SiC) wafers by commonly used abrasive wire saw method is very time and cost consuming due to its extreme high hardness. This problem becomes more serious with the increase of SiC ingot diameter. Therefore, electrical discharge machining (EDM), which is a thermal process regardless of workpiece hardness, is developing as an alternative method for slicing SiC. In this study, EDM of SiC by a foil tool electrode was proposed for slicing SiC. Comparative experiments of foil EDM of SiC between in deionized water and in EDM oil were conducted. The tool electrode wear ratio, area cutting speed, kerf width, and surface integrity were experimentally investigated, and the reasons for the differences were discussed. It was clarified that foil EDM in deionized water can attain a higher cutting speed than that in EDM oil under the same machining conditions. However, the surface roughness and tool wear ratio were larger than in EDM oil. Short pulse duration was found to be more suitable for EDM of single crystal SiC in both dielectric liquids.

Machining Technology of Ultrasonic Assisted Grinding for a Silicon Carbide Wafer Carrier

The machining technology of ultrasonic assisted ductile mode grinding for the silicon carbide (SiC) wafer carrier. The machining tool is designed and analyzed by ANASYS 14.0 and the machining technology is studied for the 6-inch SiC wafer carrier. The ultrasonic tool holder with the resonance frequency 26 kHz is designed and fabricated. The advantageous machining parameters are proposed that spindle rotation rate is 3000 rpm, feed speed is 200 mm/min, and ultrasonic output power is 250 W. The measurement results show that the average roughness (Ra) of the SiC is 0.18 μm, the MRR is over 2.4 mm3/min, the tool tips are only minor abrasion, and the cutting temperature are reduced. Obvious, the machining technology has the advantage of high surface quality, high machining efficiency and long tool life.

Formation of graphite/sic structures by the thermal decomposition of silicon carbide

The conditions in which carbon layers are synthesized on the surface of silicon carbide (SiC) wafers by thermal decomposition are studied. The effect of temperature and composition of the gas atmosphere on the structural properties of the layers being synthesized is analyzed. The conditions in which continuous graphite films with both single-crystal and polycrystalline structure can be obtained are determined.

OS0601 レーザダイシングにおける加工条件がSicウェハの加工精度に及ぼす影響

Silicon carbide (SiC) is a promising wide-bandgap semiconductor for future power electronics and system applications. However, high-efficient and ultra-precise dicing of SiC remains a challenge due to its extremely high hardness and brittleness. Investigation of the influence of laser processing parameters on cut quality of laser diced SiC wafer can improve efficiency and precision. In this work, 4H-SiC wafers were processed with multi-passes of a CO_2 continuous laser source. The influence of the laser power and scanning speed on the cut quality was evaluated. The experimental results showed that it was possible to obtain a smooth surface, with average arithmetic roughness as small as 0.56μm at effective speed as fast as 1.25mm/s.

Ion beam evaluation of silicon carbide membrane structures intended for particle detectors

Thin ion transmission detectors can be used as a part of a telescope detector for mass and energy identification but also as a pre-cell detector in a microbeam system for studies of biological effects from single ion hits on individual living cells. We investigated a structure of graphene on silicon carbide (SiC) with the purpose to explore a thin transmission detector with a very low noise level and having mechanical strength to act as a vacuum window. In order to reach very deep cavities in the SiC wafers for the preparation of the membrane in the detector, we have studied the Inductive Coupled Plasma technique to etch deep circular cavities in 325μm prototype samples. By a special high temperature process the outermost layers of the etched SiC wafers were converted into a highly conductive graphitic layer. The produced cavities were characterized by electron microscopy, optical microscopy and proton energy loss measurements. The average membrane thickness was found to be less than 40μm, however, with a slightly curved profile. Small spots representing much thinner membrane were also observed and might have an origin in crystal defects or impurities. Proton energy loss measurement (also called Scanning Transmission Ion Microscopy, STIM) is a well suited technique for this thickness range. This work presents the first steps of fabricating a membrane structure of SiC and graphene which may be an attractive approach as a detector due to the combined properties of SiC and graphene in a monolithic materials structure.

Design tools adapting to new materials

GaN on silicon carbide wafers, produced for the European Space Agency's GREAT2 project to develop GaN technology for space application. The growing use of silicon alternatives such as gallium nitride and silicon carbide is forcing changes in electronic modelling and design software.

Wet Processing for Post-epi & Pre-furnace Cleans in Silicon Carbide Power MOSFET Fabrication

Silicon carbide (SiC) device fabrication technology shares many similarities with Si manufacturing, but identifying whether material differences affect cleaning capability is of interest for this growing field. Material parameter differences include diffusion coefficients, surface energy, and chemical bond strength, all of which can play a role in cleaning critical surfaces. This work compares trace surface contamination levels (as measured by TXRF) after 100 mm or 150 mm 4H SiC wafers underwent mercury-probe capacitance voltage (MCV) mapping, to levels after subsequent cleans. Trace levels of metals such as Hg, Fe, and Ni were controllably added during MCV, and it was shown that a variety of cleaning approaches can return the SiC surface to sub-5x1010 atoms/cm2 levels of cleanliness. Where these cleans fit into an integrated device process flow and comparison of cost are discussed.

Carbon fluoroxide nanoparticles as fluorescent labels and sonosensitizers for theranostic applications

Carbon fluoroxide (CFO) nanoparticles (NPs) produced from silicon carbide wafers are used as both fluorescent probes and sonosensitizers for theranostic application. In vitro cell tests were carried out to investigate the feasibility of ultrasound-based therapy with the use of the CFO NPs. The NPs that penetrated inside the cells were shown to provoke cell destruction after application of an ultrasound treatment. No significant toxic effect was observed when the cells were treated with NP concentrations up to 0.5 mg ml−1 without applying ultrasound treatment. The obtained results open a new way toward cancer therapy strategies.

Wet Processing for Post-epi & Pre-furnace Cleans in Silicon Carbide Power MOSFET Fabrication

Silicon carbide (SiC) power devices provide improved switching efficiency and are well-suited for high temperature, and medium to high voltage applications. As such, they are expected to spur growth for applications >1000V over the next decade as they enable significant reduction in emissions [1]. The chemically inert nature of SiC presents unique opportunities and challenges with regard to cleaning and surface preparation for fabrication of power metal-oxide-semiconductor field-effect transistors (MOSFETs). SiC processing often leverages learning from ultra-large-scale integration (ULSI) Si, but exposing where that experience can be directly transferred or must be modified is part of the charter for the SiC fabrication community. Here we present results for cleans post-epi test, also known as initial wafer clean (IWC), and prefurnace clean based on concentrated chemistries developed for Si, and discuss cost tradeoffs as the technology ramps from pilot to volume production. Although the diffusion of metals in single-crystal SiC is much slower than that found in silicon (Si) for similar temperatures, SiC thermal processing generally occurs at much higher temperatures and therefore metal contamination must be minimized to maintain process control and reliability. Iron, nickel, and other metallics are understood to degrade intrinsic lifetime of gate oxides, so are monitored for SiC processing at levels comparable to appropriate Si technology nodes. W-anode TXRF is an effective diagnostic tool used in controlling these contaminants, so is employed by measuring Si and SiC monitor wafers run alongside device lots at appropriate process steps. TXRF was performed at EAG in a Technos TREX model instrument. Additionally, 1200V SiC MOSFETs are fabricated on epitaxially grown N- layers and typically characterized with mercury (Hg) probe capacitance-voltage (MCV), leaving trace levels of Hg on the SiC wafer surface. In addition to the typical metal concerns, Hg must be removed before wafers proceed into the fabrication process flow. For this study, 100mm SiC wafers were Hg probed in a Semilab MCV-530 tester, utilizing a multi-measurement pattern of 44 points. Trace levels of Hg were analyzed with mapping-mode Mo-anode TXRF before and after a variety of cleans to provide a basis for comparison. Concentrated ULSI Si cleans (SC1, SPM, DHF, etc) with appropriate station segregation were shown to be an effective surface preparation approach for both the prefurnace clean and IWC evaluations. Iron mapped with W-anode TXRF is often measured below 1e10 atoms/cm2, representing control of Fe at or below levels identified by ITRS for Si nodes ~180nm [2], quite acceptable for the relatively thick gate oxides (~50nm SiO2) and critical feature sizes required in power semiconductor fabrication. For the IWC study, mapped Hg levels measured with Mo-anode TXRF on SiC were shown to be reduced from a typical average value of 2.5e14 atoms/cm2, and typical maximum value of 2.4e15 atoms/cm2 immediately after post-epi test, to levels below the 300-second detection limit of 7e10 atoms/cm2. In the extended paper we will discuss prefurnace cleans in the context of control charting for pilot volume manufacturing, and compare a variety of cleans at IWC; including dilute mixtures, to evaluate improvements in cost effectiveness through reduction of chemical consumption and environmental impact. Research was sponsored by the NY Power Electronics Manufacturing Consortium. The views and conclusions contained in this document are those of the authors and should not be interpreted as representing the official policies, either expressed or implied, of NY Power Electronics Manufacturing Consortium or the state of New York. [1] E. Vivrey, “Wide Band Gap Power Electronics: A Path Toward CO2 Emission Decrease”, Semicon West TechXPOT, July 10th, 2014. [2] International Technology Roadmap for Semiconductors, 2000 Update, Front End Process, http://www.itrs.net

Realization and Characterization of Graphene on 4H-SiC for Tera-Hertz Transistors

Few layers graphene has been grown on 4H-SiC. Since this material has outstanding electronic properties, we aimed fabricating graphene field-effect transistors on silicon carbide wafer. Growth of the graphene layers was made by e-beam sublimation of silicium under ultra high vacuum (UHV). These layers were patterned and used as channels of transistors with source and drain made of P+ SiC. The different technological steps were checked through Raman spectroscopy, Scanning Electron Microscopy (SEM), and electrical characterizations.

Study on Formation of Dislocation Contrast in 4H-SiC Wafer in Mirror Projection Electron Microscopy Image

A mirror projection electron microscopy (MPJ), non destructive, high spatial resolution and high throughput method, is useful for defect inspection in silicon carbide (SiC) wafer. Previously, it was demonstrate that three type of typical dislocations in 4H-SiC, threading screw dislocation (TSD), threading edge dislocation (TED) and basal plane dislocations (BPD) can be identified in MPJ image. Origin of the contrast of dislocations in MPJ image was revealed by observation of the same wafer at as-grown and after CMP processing. Streak of TSD spot is due to surface morphology, and the contrast of BPD isn’t due to surface morphology but due to charging on dislocation line.

Planarization of 6-Inch 4H-SiC Wafer Using Catalyst-Referred Etching

Catalyst-referred etching (CARE) is a planarization method based on the chemical etching reaction, which does not need abrasives. In this paper, CARE was applied to the planarization of 6-inch silicon carbide (SiC) wafers, and removal properties were investigated. The etching rate was about 20nm/h, which is almost equal to that of 2-inch SiC wafer (16 nm/h). The rms roughness was reduced along with the removal depth, and step-terrace structure was observed in whole area of the on-axis wafer surface.

Effect of Surface Damage on SiC Wafer Shape

The flatness of a silicon carbide wafer in terms of bow and warp is the result of the combination of factors both material and process related. Sub-surface damage (SSD) from the wafering process steps can be considered as a thin film under compressive stress on the wafer surface. SSD is generally decreased with each subsequent processing step after the multiwire saw. Single-sided process steps can produce very different levels of SSD on opposing wafer surfaces, leading to high bow and warp values. The present study investigates the effects of SSD on wafer flatness at various process steps as well as methods to minimize shape effects due to SSD during and after processing.

Relations between Surface Morphology and Dislocations of SiC Crystal

We observed fine surface morphology of silicon carbide wafers using a low energy scanning electron microscope (LESEM). Typical kinds of surface defects were observed by LESEM. After low temperature KOH treatment, it is confirmed that positions of etch pits are the same positions of these defects. Correlation between LESEM imaging and cross-sectional scanning transmission electron microscopy (STEM) of the same defects reveals threading dislocations and basal plane dislocations at the core of the defects.

High-efficiency impurity activation by precise control of cooling rate during atmospheric pressure thermal plasma jet annealing of 4H-SiC wafer

We have investigated high-temperature and rapid annealing of a silicon carbide (SiC) wafer by atmospheric pressure thermal plasma jet (TPJ) irradiation for impurity activation. To reduce the temperature gradient in the SiC wafer, a DC current preheating system and the lateral back-and-forth motion of the wafer were introduced. A maximum surface temperature of 1835 °C within 2.4 s without sample breakage was achieved, and aluminum (Al), phosphorus (P), and arsenic (As) activations in SiC were demonstrated. We have investigated precise control of heating rate (Rh) and cooling rate (Rc) during rapid annealing of P+-implanted 4H-SiC and its impact on impurity activation. No dependence of resistivity on Rh was observed, while increasing Rc significantly decreased resistivity. A minimum resistivity of 0.0025 Ω·cm and a maximum carrier concentration of 2.9 × 1020 cm−3 were obtained at Rc = 568 °C/s.

Surface activated bonding of GaAs and SiC wafers at room temperature for improved heat dissipation in high-power semiconductor lasers

Thermal management of high-power semiconductor lasers is of great importance since the output power and beam quality are affected by the temperature rise of the gain region. Thermal simulations of a vertical-external-cavity surface-emitting laser by a finite-element method showed that the solder layer between the semiconductor thin film consisting of the gain region and a heat sink has a strong influence on the thermal resistance and direct bonding is preferred to achieve effective heat dissipation. To realize thin-film semiconductor lasers directly bonded on a high-thermal-conductivity substrate, surface-activated bonding using an argon fast atom beam was applied to the bonding of gallium arsenide (GaAs) and silicon carbide (SiC) wafers. The GaAs/SiC structure was demonstrated in the wafer scale (2 in. in diameter) at room temperature. The cross-sectional transmission electron microscopy observations showed that void-free bonding interfaces were achieved.