Silicon Carbide MOSFETs Research Articles

Design of Ultracompact Gate Driver Integrated With Current Sensor and Commutation Path for a 211-kW Three-Level SiC Aircraft Propulsion Inverter

The aviation industry is increasingly interested in high-efficiency and high-density electric propulsion systems enabled by high-power Silicon Carbide (SiC) modules. However, designing a high-power SiC-based multi-level inverter for aircraft faces several challenges, including high loop inductance, bulky current sensors, high-bandwidth sampling of device current, partial discharge (PD) at high altitudes, and shorter short-circuit withstanding time of SiC MOSFETs. To address these challenges, this paper proposes an ultra-compact multi-functional gate driver that integrates the driving circuit, Rogowski coil current sensor (RCCS), and commutation path for a 211-kW SiC-based three-level (3-L) propulsion inverter. The optimized commutation path and RCCS provide multiple functions, including suppressing overshoot voltage, ultra-fast short-circuit protection, and ac load current sampling. The gate driver’s electric-field can be controlled by PCB-based shielding and shaping to eliminate the PD at high altitudes, thereby improving power density and reducing insulation risk. The paper presents the design methodology of the multi-functional ultra-compact gate-driver and the board-level to system-level common-mode (CM) noise modeling and suppression. The performance of the gate driver is verified on a 211-kW 3-L altitude-ready SiC propulsion inverter system, achieving a power density of 19.5 kW/kg and 7.1 kW/L.

Parallel Connection of Silicon Carbide MOSFETs—Challenges, Mechanism, and Solutions

Parallel Connection of Silicon Carbide MOSFETs—Challenges, Mechanism, and Solutions

Structure and the Thermal Management of a 3-D Silicon Carbide MOSFET Module

Silicon carbide (SiC) device has higher switching frequency, higher breakdown voltage, and lower on-state voltage drop, which makes it subversive potential in the high power density applications. However, the traditional packaging structure cannot cope with the high power density of SiC devices, so the existing commercial SiC power module can only be used in derating applications. This paper proposed a 3-D packaging design method for high power density MOSFET power module, in which the cooling system is integrated inside the module to reduce the thermal resistance and the temperature difference of the SiC MOSFET chips. At the same time, the heat dissipation process of the new structure is modeled and analyzed, and the accuracy of the model is proved by experiment and simulation.

Study on switching behavior of silicon carbide MOSFET by gate driver

Compared with IGBT, SiC MOSFET has improved frequency efficiency, outstanding reliability which not only can achieve energy saving and loss reduction, but also increase power density and other characteristics. SiC MOSFETs are faced with countless challenges in practice because of their superior switching speed. The gate driver was adjusted in this paper to investigate the switching behavior of silicon carbide MOSFET. The switching behavior of silicon carbide devices was first characterized by simulation software using a double- pulse test bench. Different parasitic inductances, resistances and additional parameters were found to have significant impacts on SiC MOSFET switching behavior. The results are analysed after combination and comparison.

Development and Performance Evaluation of Integrated Hybrid Power Module for Three-Phase Servo Motor Applications.

This study aims to develop a 30 kHz/12 kW silicon carbide (SiC)/Si integrated hybrid power module (iHPM) for variable frequency drive applications, particularly industrial servo motor control, and, additionally, to theoretically and experimentally assess its dynamic characteristics and efficiency during operation. This iHPM integrates a brake circuit, a three-phase Si rectifier, and a three-phase SiC inverter within a single package to achieve a minimal current path. A space-vector pulse width modulation (SVPWM) scheme is used to control the inverter power switches. In order to reduce parasitic inductance and power loss, an inductance cancellation design is implemented in the Si rectifier and SiC inverter. The switching transients and their parasitic effects during a three-phase operation are assessed through an electromagnetic-circuit co-simulation model, by which the power loss and efficiency of the iHPM are estimated. The modeled parasitic inductance of the inverter is validated through inductance measurement, and the effectiveness of the simulated results in terms of switching transients and efficiency is verified using the experimental results of the double pulse test and open-loop inverter operation, respectively. In addition, the power loss and efficiency of the SiC MOSFET inverter are experimentally compared against those of a commercial Si IGBT inverter.

Humidity Robustness of 3.3kV SiC-MOSFETs for Traction Applications - Compared to Standard Silicon IGBTs in Identical Packages

Silicon carbide (SiC) MOSFETs are gaining more and more market share in typical silicon (Si) IGBT applications such as traction or renewable energies. Especially in reliability sensitive traction applications, medium voltage IGBT-modules (3.3 kV-6.5 kV) are widely used and introducing SiC-MOSFETs to such industries is the next self-evident step already on the way. While their superior electrical performance has been generally accepted already (e.g. [1]), SiC-modules have not yet established a track record of high reliability in this voltage class. For this study, 3.3kV SiC-MOSFET-switches were compared to standard Si-IGBTs regarding their humidity robustness under high voltage bias. Both chip types had been assembled in the same traction rated packages to exclude this influence. The Si-IGBTs resembled the well-known industry standard performance, while the SiC-MOSFETs show no degradation within the reported test time of 2000 h. Given the fact [2], that the latest Si-IGBT generation offers a much better humidity performance as well, the standardised HV-H³TRB is no longer sufficient to provoke failures within a reasonable testing time. On the one hand, this suggests that humidity driven failures will not be an issue under field conditions anymore. On the other hand, even harsher tests are required to investigate differences in humidity performance.

Correlation of Extended Defects with Electrical Yield of SiC MOSFET Devices

The quality of the silicon carbide (SiC) epitaxial layer, i.e., layer homogeneities and extended defect densities, is of highest importance for high power 4H-SiC trench metal-oxide-semiconductor field effect transistors (Trench-MOSFET) devices. Especially, yield for devices with a large chip area is severely impacted by extended defects. Previously, devices had to be fully manufactured to effectively gauge the impact of a reduction in extended defect densities in the epitaxial layers on device yield. The production of devices such as Trench-MOSFETs is an extensive procedure. Therefore, a correlation between extended defects in the epitaxial layer and electrical device failure would allow to reliably estimate the impact of process changes during epitaxial layer deposition on electrical device yield.For this reason, n-type epitaxial layers were grown on around 1,000 commercially available 150 mm 4H-SiC Si-face substrates, which received a chemical wet cleaning prior to the epitaxy deposition. Substrates with lowest micro-pipe density from two different suppliers were used. The wafers were characterized with the corresponding device layout for defects utilizing surface microscopy as well as ultraviolet photoluminescence techniques. Subsequently, these wafers were used to produce more than 500,000 Trench-MOSFET devices. All devices have been tested on wafer level for their initial electrical integrity.With these methods a precise correlation between extended defects in the epitaxial layer and electrical failures on wafer level could be found. The influence of different substrates on the defect-based yield prediction regarding the electrical yield on wafer level is discussed. Additionally, a calculated kill-ratio is presented and the severity of defect classes on initial device failure, e.g., stacking faults, and their key failures modes are discussed.

An 800-W Four-Level Supply Modulator for Efficient Envelope Tracking of RF Transmitters

Modern RF communication and electronic warfare applications require systems capable of amplifying signals with high bandwidths and high peak to average power ratios (PAPR). One technique used to meet these demands is supply modulation also known as envelope tracking where the drain voltage of the power amplifier (PA) is dynamically changed according to the signal envelope. The limiting factor with supply modulation is typically the efficiency and switching speed of the power converter. The power converter must also be capable of producing high power levels when supplying an array of PA units or a single high power transmitter. This paper demonstrates the design and characterization of a four-level discrete supply modulator with a peak output power of 800W operating at a maximum switching frequency of 10MHz. The modulator switches between four discrete voltages from 10 to 20V. GaN on silicon HEMT power transistors are selected for the switching devices after conducting a survey of commercially available silicon MOSFET, silicon-carbide MOSFET, and GaN on silicon power transistors. Trace interconnect models are developed to achieve accurate predictions of the time domain waveforms, including ringing at the switching edges. These interconnects are first analyzed using full-wave electromagnetic simulations, and then modeled with RLC networks suitable for time domain simulations. For a test signal with equal duty cycle between the four levels, an efficiency greater than 94.0% is demonstrated for average output powers exceeding 91.6W. When tracking the envelope of an 8MHz 64-QAM signal, an average efficiency of 93.5% is achieved providing a peak power of 800W.

Symmetric Circuit Layout With Decoupled Modular Switching Cells for Multiparalleled SiC mosfets

Parallel connection of silicon carbide (SiC) metal-oxide-semiconductor transistors (MOSFETs) are widely used in large-current-capacity applications or power modules. However, current imbalance caused by the tolerance of device parameters or asymmetric circuit layout is still a challenge for the reliability of the paralleled devices. The asymmetry of power circuit layout is inevitable when more than two devices are paralleled, which will lead to serious dynamic current imbalance. In this paper, an equivalently symmetric power circuit layout based on decoupled paralleled modular switching cells (MSCs) is presented. The current sharing mechanisms of typical asymmetric power circuit layouts are firstly illustrated. The layout with distributed DC decoupling capacitors turns out to have the potential to modify the current paths but requires further optimization. Based on the mechanisms, the construction of the symmetric layout with the concept of MSC is elaborated by mathematical analysis. DC decoupling capacitors are used to decouple the paralleled symmetric MSCs. Thereafter, the key considerations for the decoupling capacitors are discussed. Experiments are finally carried out to validate the analysis. The test results show that the peak current imbalance is reduced to only 4.1% by the equivalently symmetric power circuit layout, which confirms the effect of decoupled MSCs method.

Autonomous Electric Race Car Inverter Development: Revving up the future with resource efficient drive technology

As the electric drive finds its way progressively into important industry sectors like mobility, transportation, agriculture, production, and supporting services, it becomes increasingly important to have individually optimized technical solutions for the manifold applications. Therefore, a high number of engineers with interdisciplinary competencies will be needed soon to comply with the demand of the worldwide markets. A key component for an often-used variant of the electric drivetrain is the full-bridge inverter, which is subject to a wide spectrum of different requirements. In 2021, the University of Denver (DU), started a cooperation with the University of Applied Sciences Augsburg (UASA) to develop a full-bridge inverter for an autonomous, electrical Formula Student race car, using four permanent magnet synchronous machines as an all-wheel drive. To improve the performance of the race car, the inverter must be lightweight, package optimized, electromagnetic compatibility compliant, safe, and reliable when it distributes a maximum of 80 kW instantaneous power from the battery at a voltage between 420 V and 600 V individually to the four wheels. This article documents the inverter development process using silicon carbide MOSFET power modules, with the goal of using future results in the race car and the knowledge transfer for the education of engineering students. This transatlantic partnership between DU and UASA also serves as a success story for intercontinental collaborative development based on modern communication and decentralized development techniques.

Maximizing Efficiency in Smart Adjustable DC Link Powertrains with IGBTs and SiC MOSFETs via Optimized DC-Link Voltage Control

In recent years, the push towards electrifying transportation has gained significant traction, with battery-electric vehicles (BEVs) emerging as a viable alternative. However, the widespread adoption of BEVs faces multiple challenges, such as limited driving range, making powertrain efficiency improvements crucial. One approach to improve powertrain energy efficiency is to adjust the DC-link voltage using a DC-DC converter between the battery and inverter. Here, it is necessary to address the losses introduced by the DC-DC converter. This paper presents a dynamic programming approach to optimize the DC-link voltage, taking into account the battery terminal voltage variation and its impact on the overall powertrain losses. We also examine the energy efficiency gains of IGBT-based and silicon carbide (SiC) MOSFET-based adjustable DC-link voltage powertrains during WLTC driving cycles through PLECS and Matlab/Simulink simulations. The findings indicate that both IGBT and MOSFET-based adjustable DC-link voltage powertrains can enhance the WLTC drive-cycle efficiency up to 2.51% and 3.25% compared to conventional IGBT and MOSFET-based powertrains, respectively.

Complications of Charge Pumping Analysis for Silicon Carbide MOSFETs

Unexpected behavior is observed when charge pumping is performed on silicon carbide MOSFETs with a thermally grown silicon dioxide gate dielectric. Supported by experimental evidence, two root causes are proposed: the trap density and the channel non-equilibrium. These are difficult to overcome experimentally due to limitations by oxide breakdown and doping variation along the channel, respectively. A correct interpretation then requires a 2D model.

Impact of Temperature on Neutron Irradiation Failure-in-Time of Silicon and Silicon Carbide Power MOSFETs

Accelerated neutron tests on silicon (Si) and silicon carbide (SiC) power MOSFETs at different temperatures and drain bias voltages were performed at the ChipIr facility (Didcot, UK). A super-junction silicon MOSFET and planar SiC MOSFETs with different technologies made by STMicroelectronics were used. Different test methods were employed to investigate the effects of temperature on neutron susceptibility in power MOSFETs. The destructive tests showed that all investigated devices failed via a single-event burnout (SEB) mechanism. Non-destructive tests conducted by using the power MOSFET as a neutron detector allowed measuring the temperature trend of the deposited charge due to neutron interactions. The results of the destructive tests, in the −50 °C–180 °C temperature range, revealed the lack of a common trend concerning the FIT temperature dependence among the investigated SiC power MOSFETs. Moreover, for some test vehicles, the FIT-temperature curves were dependent on the bias condition. The temperature dependence of the FIT values, observed in some SiC devices, is weaker with respect to that measured in the Si MOSFET. The results of the non-destructive tests showed a good correlation between the temperature trends of the deposited charge with those of FIT data, for both Si and SiC devices.

Gallium Nitride Power Devices in Power Electronics Applications: State of Art and Perspectives

High-electron-mobility transistors based on gallium nitride technology are the most recently developed power electronics devices involved in power electronics applications. This article critically overviews the advantages and drawbacks of these enhanced, wide-bandgap devices compared with the silicon and silicon carbide MOSFETs used in power converters. High-voltage and low-voltage device applications are discussed to indicate the most suitable area of use for these innovative power switches and to provide perspective for the future. A general survey on the applications of gallium nitride technology in DC-DC and DC-AC converters is carried out, considering the improvements and the issues expected for the higher switching transient speed achievable.

Active Gate Driver for Dynamic Current Balancing of Parallel-Connected SiC MOSFETs

In high-power applications, parallel connection of discrete silicon carbide (SiC) MOSFETs is necessary to increase the current rating. However, the unbalanced dynamic current during switching transient may cause unequal power loss and thermal distribution, which is a great challenge in parallel applications. In this paper, a dynamic current balancing method based on a new active gate driver (AGD) is proposed to improve the current sharing. The principle of the AGD is based on <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">di/dt</i> feedback control and voltage controlled current source to adjust gate drive current of SiC MOSFETs. Therefore, the switching trajectory of the paralleled devices can be changed to achieve current balance. In addition, by using master-slave control strategy, the proposed AGD can be easily used for multiple paralleled devices. The double pulse tests are conducted to verify the effectiveness of the proposed AGD. For two paralleled devices, the turn-on and turn-off switching energy imbalances are reduced from 13.4% and 56.0% (12.1% and 52.9%) to 8.8% and 15.3% (8.0% and 8.8%) by the current source (current sink) circuit. For six paralleled devices, the degrees of turn-on and turn-off switching energy imbalances can be reduced from 21.8% and 16.1% to 11.8% and 7.8% by the proposed AGD. <fn fn-type="other" id="fn3" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> This work was supported by Key-Area Research and Development Program of Guangdong Province under Grant 2021B0101310004, and the research program sponsored by Eaton. (<i>Corresponding author</i>: <i>Junming Zhang</i>) Y. He, X. Wang, S. Shao, and J. Zhang are with the College of Electrical Engineering, Zhejiang University, Hangzhou 310027, China (e-mail: ; ; ; ). </fn>

Performance and Short-Circuit Reliability of SiC MOSFETs With Enhanced JFET Doping Design

In this article, the influence of the JFET width and JFET doping concentration on the 1.2-kV planar-gate silicon carbide (SiC) MOSFETs’ static characteristics, <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> – <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> characteristics, and short-circuit (SC) reliability is discussed. With the increase of the JFET width, the specific ON-resistance decreases first and then increases (but the quasi-saturated current continues to increase), the blocking voltage decreases, and the reverse capacitance increases. The SC tests under 400-V dc bus voltage are carried out to compare the SC capability of the devices. With the increase of the JFET width, the SC peak current first increases and then decreases, and the SC withstanding time keeps decreasing. The increase of peak current is due to the weaker electric field shielding effect by the P-well. With the further increase of the JFET width, the peak current decreases because the depletion layer appears in the middle position of the JFET region below the gate oxide and the channel density decreases with the wider JFET width. Compared with the winner of the traditional design, the winner with enhanced JFET doping is preferred because it achieves an increased Baliga’s figure of merit (BFOM) by 15.9% and 1/high-frequency figure of merit (HF-FOM) by 84.2% without sacrificing too much SC reliability, which is more competitive.

Comparative analysis and improved design of LLC inverters for induction heating

AbstractThis work presents a comparative analysis and design procedure of a converter based on an LLC resonant inverter used for induction heating applications depending on the transistor technology used and the selected operating frequency. A major objective of the work is to determinate the inverter design requirements leading to the optimal sizing of the components, improving its operation and minimizing power losses. Additionally, it proposes a design to obtain a great insensitivity of the inverter operation against large variations of load impedance. This article analyzes the operation of the inverter where the power regulation is carried out by phase‐shift (PS) modulation. Simple rules are formulated for the design of the resonant circuit components. The design has been verified testing a 25‐kW inverter in an industrial application of induction hardening operating at 500 kHz. Inverter efficiency is around 98.5% when using Silicon Carbide (SiC) MOSFETs.

Effects of 5 MeV proton irradiation on 4H-SiC lateral pMOSFETs on-state characteristics

Silicon carbide (SiC) MOSFETs are often used in harsh environments where they are exposed to ionizing radiation. This paper investigates the effects of high-energy proton irradiation on SiC MOSFETs, with a particular emphasis on the on-state characteristics of lateral pMOSFETs. By comparing with the lateral 4H-SiC nMOSFET after irradiation in our prior work, we observed the deviations of important electrical parameters. As the irradiation dose increases, the threshold voltage (VTH) of pMOSFETs is negatively shifted and has more negative offsets than that of nMOSFETs. This is due to two factors which affect VTH after irradiation: the near interface oxide traps (NIOTs) and the interface traps (Nit). These two factors compensate each other for nMOSFETs, but strengthen each other for pMOSFETs. It is found that an increase in the density of interface traps (Dit) in both types of MOSFETs after irradiation. However, unlike the nMOSFET, the pMOSFET has a decreasing field effect mobility (μFE) with the increase of irradiation dose. We believed that besides the effect of Dit on μFE, NIOTs have a more profound influence on μFE, resulting in different changes between nMOSFETs and pMOSFETs’ μFE.

An Integrated Gate Driver Based on SiC MOSFETs Adaptive Multi-Level Control Technique

In HV (high-voltage) and HF (high-frequency) applications, SiC (silicon carbide) MOSFET is widely used for its small parasitic characteristics and fast switching speed. Using discrete devices on PCB, the active gate driver is usually adopted to restrict EMI (electromagnetic interference) noise. This method could achieve a limited switching performance improvement, and many disadvantages still exist. In this paper, the integrated adaptive multi-level gate driver is presented to improve the switching performance of SiC MOSFET in HV and HF applications. The proposed gate driver is realized on the chip using critical techniques such as <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dV/dt</i> noise attenuation, high-speed circuit, and anti-false triggering mechanism. Then, the proposed gate drive is fabricated in a 0.18 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$</tex-math> </inline-formula> m BCD process and occupies a 4.16 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{2}$</tex-math> </inline-formula> active area. The experimental results show that SiC MOSFET can achieve a 200 ns switching time, 0.8 mJ energy losses, no more than 15 V/ns average <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dV/dt</i> noises, and 1.5 A/ns average <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">di/dt</i> noises under a 600 V power supply and a 33 A load. SiC MOSFET can also realize the excellent switching performance at different load currents from 15 A to 90 A by using the proposed adaptive multi-level gate driver.

Online Junction Temperature Estimation Method for SiC MOSFETs Based on the DC Bus Voltage Undershoot

Silicon carbide (SiC) power devices are promising in industrial applications. Junction temperature monitoring is greatly significant for improving the reliability of devices and systems. However, state-of-the-art SiC MOSFET junction temperature estimation methods generally have drawbacks of low resolution, difficult measurement, and complicated installation. In this article, a novel junction temperature estimation for SiC MOSFETs based on the dc bus voltage undershoot is proposed. The correlation between junction temperature and current change rate is analyzed and verified by experiments. The current change rate of each SiC MOSFET can be measured via the dc bus voltage undershoot because of the stray inductance of the bus commutation loop. The undershoot of the dc bus voltage during the turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> transient displays a linear dependence on the junction temperatures of the corresponding SiC MOSFET. Hence, the dc bus voltage undershoot can be utilized for monitoring the junction temperatures of two SiC MOSFETs in the half-bridge. Besides, practical implementation and estimation errors are presented. The method proposed has high accuracy and resolution for junction temperature monitoring. Besides, the method proposed can reduce the complexity, size, and cost of the monitoring circuit. Moreover, the method proposed is noninvasive and easy to install. It is promising for SiC MOSFET junction temperature monitoring in practical applications.