Silicon Carbide MOSFETs Research Articles

A Highly Integrated Multichip SiC MOSFET Power Module With Optimized Electrical and Thermal Performances

This paper proposes a highly integrated multichip silicon carbide (SiC) MOSFET power module packaging with optimized electrical and thermal performances. The structure of the module is to stack the two power switches up and down with the cooling system and the decoupling circuit integrated inside the module. The structural characteristics of the module realize the co-optimization of the switching performance, thermal management, and electromagnetic interference (EMI) issue of the multichip SiC module, which effectively solve the contradiction in the optimization of the electrical and thermal performance. In addition, by optimizing the process flow and designing a variety of soldering fixtures, the feasibility of the process and the engineering margin is increased. Experiments and simulations show that the proposed SiC power module has good electrical and thermal performance. The loop parasitic inductance is reduced to 2.02 nH and the common-mode (CM) current is eliminated. The drain–source voltage overshoot during the turn-off transient is reduced by 76.5%, and the voltage oscillation is significantly improved due to the integration of the decoupling circuit. At the same time, the integrated liquid-cooling heatsink greatly improves the cooling efficiency of the module on the premise of ensuring the insulation performance of the module.

Evaluation of 4H‐SiC MOSFET transfer characteristics using machine‐learning techniques

The performance of 4H silicon carbide (SiC) MOSFETs critically depends on the quality of the SiC/silicon oxide interface, which typically contains a high density of interface traps. To solve this problem, fast and reliable characterization methods are required. The commonly used evaluation schemes for 3-terminal transfer characteristics, however, neglect the presence of interface traps. Here, a method based on machine-learning techniques is presented which extracts reliable performance parameters from transfer characteristics of 4H-SiC MOSFETs including a quantitative estimate of the density of interface traps. This method is successfully validated by comparison with Hall-effect measurements and applied to various MOSFET types.

Investigation of Unclamped Inductive Switch Characteristics in 4H-SiC MOSFETs With Different Cell Topologies

To investigate the unclamped inductive switch (UIS) characteristics, 1200 V silicon carbide (SiC) planar MOSFETs with four cell topologies of linear, current sharing linear, square, and hexagon are designed and manufactured. The experimental platform was built and tested. The results show that the single pulse avalanche energy density of the linear cell topology is 1.69 times higher than that of the square and 1.49 times that of the hexagon. Further, the UIS process is simulated by using physical simulation, which shows that the avalanche energy was concentrated near the corner of the P-base region in the UIS mode. From this, the avalanche energy distribution differences of the four cell topologies were analyzed and compared. A theoretical model of avalanche heating per unit area is proposed, which shows that the avalanche energy density is inversely proportional to the proportion of avalanche energy concentration region. This study may contribute to the cell topology design of SiC MOSFETs under the application scenario with high avalanche reliability requirements.

An Accurate Analytical Model of SiC MOSFETs for Switching Speed and Switching Loss Calculation in High-Voltage Pulsed Power Supplies

Nanosecond output pulse and high efficiency are achieved in high-voltage pulsed power supplies (HVPPSs) by applying silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors ( <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s), whose switching speed and switching loss are two vital characteristic parameters. However, the existing research on switching characteristics of SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s is mainly based on the double pulse test circuits with inductive loads, which is not suitable for assessing the devices in HVPPSs with resistive loads. Besides, some simplified analytical methods in HVPPSs lead to poor precision. To accurately predict the switching behavior of SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s in HVPPSs for guiding the design of gate driving circuits and power loops, this article proposes an accurate analytical model considering parasitic inductances, nonlinear parasitic capacitances, transfer characteristic, and output characteristics of SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s. High-precision fitting of transfer characteristic is realized by using the Gaussian function. Besides, the dynamic parasitic gate-drain capacitance is measured by experiment, and three-dimensional curve fitting is performed on the output characteristics to exactly represent <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> -resistance. Furthermore, switching speed and switching loss can be directly calculated according to the solved state variables. Finally, the analytical model is verified by experiment, and the effects of gate driving circuits and power loops on switching characteristics are researched in detail.

Avalanche capability degradation of the parallel-connected SiC MOSFETs

Silicon carbide (SiC) MOSFET chips are often connected in parallel in a module to increase the current rating. However, the current capability is degraded due to unbalanced current and temperature distributions which affect the avalanche processes particularly in extreme operating conditions. To obtain the root cause of the degradation and identify the dominant factors, single-pulse avalanche testing is carried out in this study, and TCAD simulation is used for mechanism analysis. It is revealed that electrothermal parameters have different effects on current sharing in different stages of avalanching. The corresponding failure mechanisms are analyzed, and the main cause of avalanche failure with parallel devices is found to be the difference in breakdown voltage. Device with smaller BV shares more current as well as more heat, which fails first eventually. To resolve such issues, proper device screening/paring should be carried out. The findings are helpful for a better understanding of avalanche capability degradation in parallel devices application.

On-Chip Active Turn-Off Driving Technique to Prevent Channel Current From Disappearing Prematurely in SiC MOSFET’s Applications

Silicon carbide (SiC) MOSFET has significant advantages in high-voltage (HV) and high-frequency (HF) applications due to its electrical characteristics. In order to make use of its merits, the active driver is necessary for SiC MOSFET. During the turn-off operation of SiC MOSFET, it is critical to prevent the channel current from disappearing prematurely, which has not been addressed in existing active drivers. This brief proposes an on-chip active turn-off driver to realize the fast turn-off speed and low EMI noises. The mechanism is that the turn-off driving current needs to be adjusted rapidly according to the operating state of SiC MOSFET, which can also ensure that EMI noises and overshoots are under control. Then, the proposed turn-off driver is fabricated in a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.18~\mu \text{m}$ </tex-math></inline-formula> BCD process and occupies a 0.99mm2 active area. Finally, using the proposed active turn-off driver, the turn-off operation of SiC MOSFET has experimented with the 15A and 90A load current, respectively. SiC MOSFET realizes a high turn-off performance, about 200ns turn-off time with low EMI noises, demonstrating that the proposed on-chip active turn-off driving technique is suitable for SiC MOSFET under different loads.

Integrating 10-kV SiC MOSFET Into Battery Energy Storage System With a Scalable Converter-Based Self-Powered Gate Driver

In the hardware design of battery energy storage system (BESS) interface, in order to meet the high-voltage requirement of grid side, integrating 10-kV silicon-carbide (SiC) MOSFET into the interface could simplify the topology by reducing the component count. However, the conventional gate driver design is challenging and inextensible in BESS, since the high-voltage rating and high dv/dt bring the requirements of high-voltage isolation and low common-mode capacitance. Therefore, in this article, a scalable converter-based self-powered (SCS) gate driver is further proposed. A 5-kV input power extracting converter based on a voltage-balanced SiC MOSFET stack is constructed to self-power the gate driver, which exhibits simplification of basic topology and sufficient gate driver power handling capability regardless of the switching requirement of main loop power device. Besides this, the power extracting converter is designed to act as a clamping resistor-capacitor-diode (RCD) snubber circuit, which makes the SCS gate driver scalable to the series connection of power devices. Analysis and design consideration are given in detail, followed by the experimental verification using 10-kV/10-A SiC MOSFETs.

Core loss measurement and comparative analysis for soft magnetic materials under complex non-sinusoidal excitations

With the advancement of wide-bandgap power devices, the power electronics equipment is developing toward higher switching frequencies and more complex switching modes in recent years. Accurate prediction of the core loss for magnetic components has been emphasized as the excitations of magnetic materials varying depending on the operating mode of the power supplies. Therefore, this paper presents the results of an extensive core loss study performed on nanocrystalline alloy (FT-3KL), amorphous alloy (1K101) and ultra-thin oriented silicon steel (GT-50). Firstly, an automatic setup for core loss measurement of soft magnetic materials fed by a full-bridge inverter based on silicon carbide (SiC) MOSFET is proposed. Then, the effects of switching oscillations from the inverter and the characteristic parameters of complex non-sinusoidal excitations on the core loss are analyzed comparatively. The core loss shows different regular distributions with the change of each characteristic parameter of excitations respectively. However, the regular distributions will be influenced by the high-frequency switching oscillations, which makes the prediction of core loss more complicated. This paper can provide a reference for the development of high-precision core loss model and performance optimization of power electronics equipment.

Ultrafast Protection of Discrete SiC MOSFETs With PCB Coil-Based Current Sensors

Silicon carbide (SiC) <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s offer significant advantages in terms of improved efficiency and reduced size of power electronic converters. However, they possess lesser short-circuit withstand time than silicon devices. An ultrafast short-circuit protection scheme for TO-247 packaged SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s is presented in this article. The protection scheme utilizes printed circuit board (PCB) coils to sense the rate of change of current through SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s in a half-bridge circuit. The PCB coils are fabricated near a single interconnect trace between the power device and the dc busbar. To ensure minimal intrusion inside the power-loop, the methodology of selecting the minimum trace length for a desired mutual inductance between the coil and the interconnect trace is presented through finite-element analysis. Experimental results for an SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> subjected to a hard switched fault and a fault under load are presented, and the protection circuit response time under 25 ns is reported. Lastly, the peak current-mode control of a buck converter is implemented using the designed PCB coil-based sensor as current feedback sensor. Therefore, the PCB coil is demonstrated to be an effective alternative for Hall effect and magnetic core-based sensors in current control applications with dc/dc converters.

Parameter extraction and selection for a scalable N-type SiC MOSFETs model and characteristic verification along with conventional dc-dc buck converter integration.

Most silicon carbide (SiC) MOSFET models are application-specific. These are already defined by the manufacturers and their parameters are mostly partially accessible due to restrictions. The desired characteristic of any SiC model becomes highly important if an individual wants to visualize the impact of changing intrinsic parameters as well. Also, it requires a model prior knowledge to vary these parameters accordingly. This paper proposes the parameter extraction and its selection for Silicon Carbide (SiC) power N-MOSFET model in a unique way. The extracted parameters are verified through practical implementation with a small-scale high power DC-DC 5 to 2.5 output voltage buck converter using both hardware and software emphasis. The parameters extracted using the proposed method are also tested to verify the static and dynamic characteristics of SiC MOSFET. These parameters include intrinsic, junction and overlapping capacitance. The parameters thus extracted for the SiC MOSFET are analyzed by device performance. This includes input, output transfer characteristics and transient delays under different temperature conditions and loading capabilities. The simulation and experimental results show that the parameters are highly accurate. With its development, researchers will be able to simulate and test any change in intrinsic parameters along with circuit emphasis.

High‐speed high‐voltage solid‐state Marx generator based on SiC MOSFETs

AbstractThis paper presents a high‐speed, high‐voltage, solid‐state Marx generator based on silicon carbide MOSFETs. The objective was to develop a high‐rate repetitive, short‐pulse, high‐voltage and efficient generator for medical particle accelerator applications. To achieve this goal, a 720 kV Marx generator forming from 1445 kV stages was designed. Each stage includes several SiC devices in series to reach desired voltage and speed. Compared to the existing Marx generators, the proposed Marx generator is capable of producing shorter pulses with higher voltage. We present the experimental results of a three‐stage prototype Marx generator capable of producing 15 kV at 40 A output with a 200 nS pulse with a repetition rate of 500 Hz.

A New 4H-SiC Trench MOSFET With Improved Reverse Conduction, Breakdown, and Switching Characteristics

In this article, a recessed source trench silicon carbide (SiC) MOSFET with integrated MOS-channel diode (MCD) is proposed and investigated by TCAD simulations. The MCD features a short channel, and the channel length could be adjusted by varying the recessed depth. Owing to the drain-induced barrier lowering effect, a low potential barrier for electrons to flow through the JFET region to the N+ source region is formed, which successfully eliminates the bipolar degradation of the parasitic body p-i-n diode. Besides, the recessed source trench introduces an additional depletion region and homogenizes the distribution of the OFF-state electric field. As a result, a low gate-to-drain capacitance and a high breakdown voltage (BV) are obtained. Simulation results indicate that compared with the SiC trench MOSFET with integrated self-assembled three-level protection Schottky barrier diode, a 78.7% reduction in gate-to-drain capacitance and a 24.4% improvement in BV could be achieved in the proposed SiC MOSFET.

Investigation Into Active Gate-Driving Timing Resolution and Complexity Requirements for a 1200 V 400 A Silicon Carbide Half Bridge Module

Silicon Carbide MOSFETs have lower switching losses when compared to similarly rated Silicon IGBT, but exhibit faster switching edges, larger overshoots and increased oscillatory switching behaviour, resulting in greater electro-magnetic interference (EMI) generation. Active Gate Drivers (AGD) can help mitigate these issues while maintaining low switching losses. Numerous AGD topologies have been presented with varying capabilities in terms of timing resolution and output stage complexity. This paper presents an experimental investigation into the influence these capabilities have on the switching performance of an AGD driven high current module, with the goal of advising future AGD designers on the performance trade-offs between signal resolution and complexity. A 2.5 ns resolution 6-level AGD was utilised in combination with parameter sweeps and a genetic algorithm to determine gate voltage patterns that provided improved switching performance. Results indicate that higher resolution (2.5-5 ns) provided the greatest improvements in switching performance, even utilising the simplest considered gate driving patterns, with the use of more complex patterns offering minimal additional improvements. However, at lower timing resolutions (10-40 ns) a stronger set-point dependence degradation in switching performance is observed when using simpler gate patterns, which can be mitigated by utilising more complex patterns.

Investigation Into the Third Quadrant Characteristics of Silicon Carbide MOSFET

Owing to the superior performances, silicon carbide (SiC) metal oxide semiconductor field effect transistors ( <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s) attract a lot of attention. To increase the power density, it is desired to use the third quadrant (3rd-quad) characteristics of the <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> rather than the externally paralleled Schottky diode for freewheeling during the deadtime. It has been known that the 3rd-quad is far more than a body diode, and the MOS channel is also an important part of it. The channel may be not fully closed and, therefore, play a significant role in the reverse conduction even when the gate is zero or negatively biased. However, a comprehensive study of the 3rd-quad characteristics is still to be conducted. In this article, experiments and simulations are conducted and a physical model is developed to explain the 3rd-quad characteristics of the SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> . It reveals how and why the 3rd-quad characteristics are affected by the gate voltage and the junction temperature. This article is helpful for not only the application of SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> but also the device design.

Performance Evaluation of SiC-Based Two-Level VSIs with Generalized Carrier-Based PWM Strategies in Motor Drive Applications

Currently, silicon carbide (SiC) MOSFETs are several times higher in cost than the equivalent silicon (Si)-IGBTs; however, the gains in power conversion efficiency, simplification of thermal management, and energy savings in general bring the advantages of lower total cost of ownership. The implementation of discontinuous PWM (DPWM) techniques for controlling the motor drive brings further reductions for the semiconductor switching losses; however, most existing techniques have limited performance on the optimized clamping region, particularly at a low power factor, which is a common operation condition for motor drives employing the widely used V/f control, particularly at partial- or low-load conditions. This paper evaluates the performance of a SiC-based two-level voltage-source inverter (2L-VSI) motor drive operated with generalized carrier-based PWM methods. Theoretical analysis and experimental measurements are conducted in a 2.2 kW heatsink-less 2L-VSI prototype and induction machine, which demonstrates that the minimum switching losses DPWM (MSL-DPWM) is the most favorable solution in practice in terms of the achievable power conversion efficiency and harmonic distortions and also produces the least common-mode current, which is critical in motor drives.

A Novel Isolated Resonant Gate Driver With Adjustable Duty Ratio for SiC MOSFET

Resonant gate driver is a promising technique to save gate driver loss at high switching frequencies to further promote the integration level of gate driver with power modules. State-of-the-art isolated resonant gate drivers (RGDs) have to keep duty ratio fixed at 0.5 to avoid transformer saturation, which significantly limits the practical applications. A new isolated RGD (IRGD) with adjustable duty ratio to drive silicon carbide (SiC) MOSFET is proposed in this article by employing switching period expansion technique with a dual-secondary transformer. Transformer secondary windings are involved in the turn-on and turn-off processes alternatively and are switched at the falling edge of each input driving cycle. The effective switching frequency at gate driver transformer is reduced to 1/2 to further save power losses at high switching frequencies. This article further discusses the optimal damping approach to suppress <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$v_{\mathrm {gs}}$ </tex-math></inline-formula> overshoot and oscillation due to an adjacent second driving stage brought by parasitic gate resistor for IRGDs. The proposed IRGD is built with printed circuit board (PCB) integrated planar transformers, designed at leakage inductance of 303 nH with primary-side silicon (Si) devices and secondary bidirectional gallium nitride (GaN) devices. The duty ratio is proven to be adjusted from 0.15 to 0.9. The power consumption of the prototype is 0.883 W at 500 kHz and 1.473 W at 1 MHz driving a 900-V SiC device with 87-nC gate charge, which is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$6\times $ </tex-math></inline-formula> less power consumed than a conventional gate driver (CGD). The adopted SiC power device achieves dv/dt on of 18 V/ns and dv/dt off of 35 V/ns with the proposed IRGD.

Analysis of SiC and SiC-Cascode MOSFET in the design of power electronics converters for more electric aircrafts

&lt;span&gt;Wideband gap (WBG) semiconductors have developed rapidly in recent years, enabling greater efficiency and power density in the design of power electronics converters for several areas of application. In this sense, this work analyzes the efficiency and specificities of silicon carbide (SiC) technologies and their cascode topology (SiC-Cascode), operating at high switching frequencies. The analyzes are performed using a Boost converter designed for conversion systems in the more-electric aircraft (MEA) context, where the alternating current (AC) power systems can operate at fixed frequency (115V/400Hz), or at variable frequency (115V/360-800Hz), such as observe in Boeing 787, and the direct current (DC) power system can operate with a DC bus of 400 V and +/-270 V are normally used. To validate the project, computer simulations were performed and a 1.0kW prototype was built in the laboratory. The performance analyses demonstrates that 97.5% of efficiency is achieved at 500 kHz switching frequency.&lt;/span&gt;

Active Gate Driver With Turn-off Delay Control for Voltage Balancing of Series–Connected SiC MOSFETs

Connecting semiconductor switches in series is a way to increase the voltage rating of a power electronic converter. However, if two switches are directly connected without any special effort, an uneven voltage between the switches can occur due to nonidentical characteristics of them. A significant voltage imbalance may destroy the switches, and both thermal and loss imbalance also lead to the unstable system. Since a silicon carbide (SiC) metal–oxide–semiconductor field–effect transistor ( <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> ) has a faster switching speed and higher voltage blocking capability than silicon (Si) devices, existing voltage balancing methods for Si devices may not be suitable. This article proposes a voltage balancing method that controls turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> delay time of the switch by adding one bipolar junction transistor (BJT) on a gate turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> path. Depending on the base voltage of the BJT, turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> resistance and delay time are actively changed which mitigates the imbalance problem. The theoretical analysis of the proposed method has been discussed in detail based on the classical <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> model. Both the simulations and experiments have been performed to verify the theory and the validity of the proposed method where the voltage imbalance is reduced from 22.4% to 3.2% as well as reducing the switching loss at the entire voltage and load conditions.

High power density thermal management of discrete semiconductor packages enabled by additively manufactured hybrid polymer-metal coolers

Discrete-packaged wide bandgap (WBG) semiconductor devices provide a flexible and cost-effective solution for scalable highly dense power electronics. However, their utilization at high power levels is limited due to various challenges, while the effective thermal management if one of them. We develop a liquid cooled thermal management solution for discrete semiconductor packages using polymer-metal hybrid cooling structure design and integration. Coolant flowing through an additively manufactured polymer manifold is guided to finned metal heat sinks having low thermal resistance and overall mass. Here, we study a number of prototypes designed for integration of silicon carbide (SiC) MOSFETs in TO-247 package. The cooling integration is benchmarked with a baseline design having an aluminum heat sink with square inline pin fins. The cooling strategy is tested experimentally with results used to validate a finite element numerical approach. Fin design parameters including fin height, thickness, spacing, and arrangement are studied to assess their impact on heat sink temperature and pressure drop. Zigzag fins showed the most promising performance when compared to straight fins, inline fins, and staggered pin fins. The zigzag design showed lower maximum temperatures at comparable pressure drop with the baseline design. The impact of thermophysical properties of the cooling fluid (water, ethylene glycol, and Novec 7300), heat sink (copper and aluminum), and electrical isolation (gap pad, aluminum nitride) are also reported. The optimal design employing zigzag fins with a copper heat sink and an aluminum nitride heat spreader achieved 32.5 % improvement in thermal performance over the baseline design with a modest 60 % increase in pressure drop and 68 % higher mass. The optimized design enables a maximum heat rejection capability of 225 W per single MOSFET package, an equivalent to 75 W/cm2 heat flux dissipation using single phase cooling.

Analysis of DC-Side Snubbers for SiC Devices Application

Due to parasitic parameters existing in Silicon Carbide (SiC) devices application, SiC devices have poor turn-off performances. SiC diode and SiC MOSFET have severe turn-off overvoltage and oscillation. The DC-side snubber is one simple suppressing method. The simplest circuit is the high-frequency decoupling capacitor in parallel with the bridge leg. However, choosing the component value is empirical. Based on the turn-off terminal impedances of the SiC diode and the SiC MOSFET, the suppressing mechanism of this DC-side snubber is analyzed. The guideline selection for the component value is provided. Furthermore, the DC-side snubber with a damping resistor is analyzed based on the terminal impedances. The design principles are provided. Finally, the validity and effectiveness of the DC-side snubbers were proven based on the double-pulse test platform.