Signal-to-noise Distortion Ratio Research Articles

Development of a low-power SAR ADC for analog front-end readout circuit of hydrophones

A low-power 16 bit 250KSa/s successive approximation analog-to-digital converter (SAR ADC) is designed. The capacitor array consists of a 2-segment sub-capacitor array and high sampling makes the coupling capacitance a unit capacitance, solving the problem of fractional capacitance mismatch. The power consumption is reduced by introducing a common-mode voltage during the switching process of the capacitor array. The circuit uses a 4-stage pre-amplifier and adds a dynamically latched comparator using output misalignment calibration to ensure high accuracy resolution. Simulated in DB Hitek 0.18 μm process, the Fast Fourier Transform(FFT) simulation results for 4096 points show that the signal-to-noise distortion ratio (SNDR) of the ADC can reach 90.2 dB and the effective number of bits (ENOB) can reach 14.69 bit. The average power consumption is 2.507mW at a supply voltage of 5 V, and this holds significant significance for the long-term deep-sea detection capabilities of sonar systems.

An 11.36-Bit 405 μW SAR-VCO ADC with single-path differential VCO-based quantizer in 65 nm CMOS

In this paper, a low-power, small-area SAR-VCO ADC is proposed using a highly linear and single-path differential VCO-based quantizer. Compared to conventional digital solution or analog design, proposed digital synthesizable dynamic voltage comparator (DVC) employs a two-stage structure, which reduces the comparator delay and offset and saves chip area. Furthermore, improved differential voltage-to-current (V–I) converter enables the realization of a single-path differential VCO-based quantizer. Trimming circuits enhance the robustness of VCO, compensating for variations induced by process variations. Additionally, a novel frequency-to-digital converter (FDC) is used as the fine quantization to directly measure the frequency. Finally, a SAR-VCO ADC is realized in 65 nm CMOS process. The simulation results show that the signal-to-noise distortion ratio (SNDR) is 70.16 dB under sampling rate of 7.8 MHz at oversampling rate (OSR) of 8. The proposed ADC has a supply voltage of 1.2V and a power consumption of 405 μW. It occupies an area of 0.16 mm2, and achieves an area figure of merit (FoMA) of 25.12 fJ*mm2/conversion-step.

A 14-bit 1-MS/s SAR ADC with a segmented capacitor array and background mismatch calibration for IoT sensing applications

A 14-bit 1-MS/s successive-approximation-register (SAR) analog-to-digital converter (ADC) for IoT sensing devices is proposed. With a VCM-based switching scheme, the 14-bit SAR ADC can lower 68.7 % switching energy consumption and 97.9 % capacitor array area by utilizing a segmented capacitor array compared to the conventional binary capacitor array. Although the root-mean-square integral nonlinearity (INL) and differential nonlinearity (DNL) of the segmented capacitor array is decreased compared with the binary capacitor array at the capacitance mismatch of 1 %, the capacitor mismatch can be background calibrated and the power consumption of the digital calibration circuit is increased by only 55.4 μW under the identical calibration step condition, and there is no noticeable deterioration in the calibration speed, resulting in a significant improvement in power efficiency. In addition, a voltage-controlled oscillator (VCO)-based comparator based on the reset-in-time technique and the adaptive stage adjustment technique is employed to further reduce power consumption. Post-simulation results show that the proposed 14-bit prototype SAR ADC can enhance the signal-to-noise distortion ratio (SNDR) and spurious-free dynamic range (SFDR) by 13.35 dB and 16.72 dB respectively at a Nyquist input rate and a sampling rate of 1-MS/s. With a power supply of 1.8 V, the power consumption is 597.8 μW with a figure of merit (FoM) value of 83.3 fJ/Conv.-step in a 0.18-μm CMOS process. The total area is 0.208 mm2, of which the analog part is only 0.038 mm2.

A calibration-free 10.7 fJ/conv.-step 12-bit 120-MS/s pipelined SAR ADC in 40nm CMOS

A calibration-free 12-bit 120-MS/s 2-stage pipelined successive approximation register (pipelined SAR) analog-to-digital converter (ADC) is presented in this paper. In asynchronous SAR ADCs, capacitive digital-to-analog converters (CDACs) are designed with bottom-plate sampling to improve sampling accuracy and split-capacitor array to save switching energy. Furthermore, both reference scaling technique and a PVT-stabilized closed-loop residue amplifier are implemented in this design to obtain an accurate inter-stage gain, enabling no additional calibration required in the pipelined SAR ADC. The prototype ADC in 40nm CMOS technology achieves a peak signal-to-noise-distortion ratio (SNDR) of 73.4 dB and 88.91dB spurious-free-dynamic-range (SFDR) at 120 MS/s sampling rate, consuming 4.88 mW power from 0.9 V supply voltage, and corresponding to an excellent figure-of-merit (FoM) of 10.7 fJ/conv.-step.

A fully-digital calibration algorithm for VCO-based ADC

In this paper, an all-digital foreground calibration algorithm is proposed to mitigate harmonic distortions in open-loop voltage-controlled oscillator (VCO)-based analog-to-digital converters (ADCs). By calculating the 3rd-order nonlinearity coefficients of the VCO-based ADC digital output, a look-up table is established to achieve nonlinearity calibration. A 40 MHz-bandwidth VCO-based ADC with 5 bit quantization and a clock frequency of 1.6 GHz was designed and simulated in 40 nm CMOS GP process, while the proposed calibration algorithm is implemented in a FPGA board. The experimental results show that the ADC signal-to-noise-distortion ratio (SNDR) is improved from 40.8 dB to 56.4 dB, and the ADC signal-to-noise ratio (SNR) is 58.9 dB, with limited hardware resources and only 104 clock cycles to converge.

A Low-power Level-Crossing ADC for Biosignal Acquisition

A large number of redundant signals will be generated when the traditional Nyquist sampling method is used to acquire a biological signal, leading to a system’s energy loss. A new level-crossing analog-to-digital converter (LC-ADC) with non-uniform sampling and fixed window structure is presented, with fewer data and low power consumption features. The circuit uses a 6-bit capacitive DAC to quantize the input signal, avoiding the error accumulation of the 1-bit capacitive DAC structure, and a nanoamp CMOS current bias circuit to provide a very low quiescent current for the comparator, further reducing power consumption. The structure was verified in a 0.18μm CMOS technology. The results indicate that the total power dissipation is 0.26uw@500Hz, the signal-to-noise distortion ratio (SNDR) is 59dB@500Hz, and ENOB reached 9.51bit, which is suitable for the acquisition of low-frequency biological signals.

An 81.6 dB SNDR 15.625 MHz BW Third-Order CT SDM With a True Time-Interleaving Noise-Shaping Quantizer

This work introduces a time-interleaved architecture to tackle the speed-resolution bottleneck of the noise-shaping (NS) successive approximation register (SAR) quantizer in a continuous-time (CT) sigma-delta modulator (SDM). A critical insight is that introducing a delay in the NS quantizer feedback loop enables complete parallelization of the NS quantizer operations. The extra time from parallelization greatly relaxes loop filtering and residue integration and enables a high quantizer resolution. Furthermore, the extra time in the feedback loop allows data weighted averaging (DWA), which eliminates the need for calibration. The prototype comprises a second-order CT front-end and a fully interleaved first-order NS quantizer. The prototype is fabricated in a 28 nm process, occupies 0.072 mm2 and consumes 6.4 mW. The peak signal-to-noise ratio (SNR), signal-to-noise-distortion ratio (SNDR), and dynamic range (DR) are 83.9, 81.6, and 84.8 dB, respectively, in a 15.625 MHz bandwidth. The corresponding Schreier SNDR figure of merit (FoM) is 175.5 dB.

Fully Digital Calibration Technique for Channel Mismatch of TIADC at Any Frequency

This paper presents a fully digital modulation calibration technique for channel mismatch of TIADC at any frequency. By pre-inputting a test signal in TIADC, the mismatch errors are estimated and stored, and the stored values will be extracted for compensation when the input signal is at special frequency which can be detected by a threshold judgement module, thus solving the problem that the traditional modulation calibration algorithm cannot calibrate the signal at special frequency. Then, by adjusting the operation order among the error estimation coefficient, modulation function and input signal in the calibration loop, further, the order of correlation and modulation in the error estimation module, the complexity of the proposed calibration algorithm is greatly reduced and it will not increase with the number of channels of TIADC. What's more, the hardware consumption of filters in calibration algorithm is greatly reduced by introducing a CSD (Canonical Signed Digit) coding technique based on Horner's rule and sub-expression sharing. Applied to a four-channel 14bit 560MHz TIADC system, with input signal at 75.6MHz, the FPGA verification results show that, after calibration, the spurious-free dynamic range (SFDR) improves from 33.47dB to 99.81dB and signal-to-noise distortion ratio (SNDR) increases from 30.15dB to 81.89dB.

On-Chip Fast Signal Generation and Low-Power SAR ADC for SiPM Readout

This article presents an ON-chip fast signal generator and a successive-approximation-register (SAR) analog-to-digital data converter (ADC) for silicon photomultiplier (SiPM) readout applications. The high-pass filter (HPF)-based fast-signal generator sharpens the rising edge of the standard SiPM output signal reducing time jitter due to the dark counts of the detector. It is implemented by leveraging the equivalent resistance of the current mirror transistor and the ac-coupling capacitor between the current mirror and the current discriminator to avoid hardware and power consumption overhead. Compared with OFF-chip solutions, the ON-chip approach eliminates the packaging pins and high-speed buffers needed for carrying the fast signals reducing packaging complexity and power consumption of the readout system. The energy quantizer utilizes the SiPM charge integrator as the ADC track-and-hold (T/H) circuit to improve the front-end power efficiency. The fast signal generator and the SAR ADC are implemented in a current-mode application-specific integrated circuit (ASIC) designed in a 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS technology. Measurement results show that the ON-chip fast signal generator is effective in improving the timing performance of the readout system. The timing resolutions are measured using SensL’s <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3\times $ </tex-math></inline-formula> 3 mm2 SiPM device with a terminal capacitance of 850 pF using an ultrashort laser pulser. Measurement results show that the fast signal generator improves the timing resolution by 23.4% compared with timing measurement using the standard output signal when the output charge is 300 pC. The ASIC achieved a measured ADC signal-to-noise-distortion ratio (SNDR) of 53.08 dB and a spurious-free dynamic range (SFDR) of 62.74 dB at 1 MS/s and a maximum front-end gain nonlinearity of 3.3% over 20–800-pC input charge range while dissipating 4.1 mW of power from a 1.8-V supply.

The design of [formula omitted]-ADC in MEMS gyro interface ASIC

This article aims at MEMS gyroscope fully differential (FD) sensing, small signal output characteristics, designs a FD third-order cascade of integrators with feedforward (CIFF) delta-sigma analog-to-digital converter (ΔΣ-ADC). Abandoning the local negative feedback in the general third-order CIFF to reduce the difficulty of layout design. And under the premise of ensuring accuracy and stability, discarding the path directly from the input to the quantizer to reduce the circuit area and the influence of harmonics on the signal-to-noise-distortion ratio (SNDR) caused by the input sampling. In order to reduce the mismatch of capacitors, the gain factor and feedforward factor are optimized, so that each factor only retains one decimal place, and all capacitors on the layout are composed of 0.2pF unit capacitors in parallel. The tape-out measurement results show that the SNDR of the ΔΣ-ADC chip is 50.13 dB in the bandwidth (BW) range of 1kHz to 11kHz, and the input signal amplitude range is 1 mV to 800 mV.

A 121 dB SNDR Zoom ADC Using Dynamic Amplifier and Asynchronous SAR Quantizer

This paper presents a discrete-time zoom analog-to-digital converter (ADC) for low-bandwidth high-precision applications. It uses a coarse-conversion 5-bit asynchronous self-timed SAR ADC combined with a fine-conversion second-order delta-sigma modulator to efficiently obtain a high signal-to-noise distortion ratio (SNDR). An integrator circuit using a high-gain dynamic amplifier is proposed to achieve higher SNDR. The dynamic amplifier uses a switched tail current source to operate periodically, simplifying the common-mode feedback circuit, reducing unnecessary static current, and improving the PVT robustness. Dynamic error correction techniques, such as redundancy, chopping, and dynamic element matching (DEM) are used to achieve low offset and high linearity. And a 2-bit asynchronous SAR quantizer with an embedded feed-forward adder is used in the second-order delta-sigma modulator to reduce the quantization noise caused by redundancy, and further achieve higher energy efficiency. Simulation results show that the ADC achieves a peak SNDR of 121.1 dB in a 390 Hz bandwidth at a 200 kHz sampling clock while consuming only 170 μW from a 2.5 V supply and the core area is 0.55 mm2. This results in a Schreier figure of merit (FoM) of 184.7 dB.

High-Speed Fully Differential Two-Step ADC Design Method for CMOS Image Sensor

The application requirements of high frame rate CMOS image sensors (CIS) in the industry have not been satisfied due to the speed limitations in traditional single-slope and serial two-step analog-to-digital converters (ADCs). In this paper, a high-speed fully differential two-step ADC design method for CIS was proposed. The proposed method was based on differential ramp and time-to-digital conversion (TDC) technology. A parallel conversion mode was formed that is different from serial conversion, and the robustness of the system was ensured due to the existence of differential ramps. Aiming at the inconsistency between traditional TDC technology and single-slope ADC, a TDC technology based on level coding was proposed. The proposed technology achieves the TDC in the last clock cycle of analog-to-digital conversion, and realized a two-step conversion process at another level. This paper presents a complete circuit design, layout design, and test verification of the proposed design method based on the 55 nm 1P4M CMOS experimental platform. Under the design environment of the analog voltage of 3.3 V, the digital voltage of 1.2 V, the clock frequency of 100 MHz, and a dynamic input range of 1.6 V, this design was a 12-bit ADC with a conversion time of 480 ns, column-level power consumption of 62 μW, differential nonlinearity (DNL) of +0.6/-0.6 LSB, and integral nonlinearity (INL) of +1.2/-1.4 LSB. Furthermore, it achieved a signal-to-noise distortion ratio (SNDR) of 70.08 dB. The proposed design provided a large area array with a high frame rate, and compared with the existing advanced single-slope ADC, its conversion speed increased by more than 52%. It provides an effective solution for the implementation of high frame frequency CIS.

Maximizing the Resolution of SAR ADC With Multisegmented DAC Using Improved MLE Calibration

Successive approximation register analog to digital converters (SAR ADCs) offer an attractive energy-efficient solution but its signal-to-noise-distortion-ratio (SNDR) is degraded due to its sensitivity to parasitic capacitance and capacitors’ mismatch. In this article, we present an improved maximum likelihood estimation (MLE) algorithm, which offers a more robust estimator for statistical-based calibration technique that can be used across different resolutions of SAR ADC. The result has demonstrated that our proposed algorithm has further improved the SNDR up to 5.86 dB for a 12–20-bit SAR ADC with multisegmented digital-to-analog converter (DAC) compared to state-of-the-art algorithms.

Digital Post-processing Techniques for Time-interleaved ADCs

This paper presents an all-digital post-processing circuit for a high-speed and high-precision time-interleaved ADC (TIADC). By pre-inputting a test signal in the TIADC, channel mismatch errors are estimated and stored, and the stored values are extracted to compensate for errors when the input signal is at a special frequency. The frequency can be detected by a threshold judgement module. This solves the problem of the traditional modulation calibration algorithm, which cannot calibrate the signal at a special frequency. A high-speed low-complexity digital down converter (DDC) circuit with an optional decimation ratio of 1, 2, 4, or 8 times was designed to have different frequency outputs of the TIADC. We applied it to a four-channel 14-bit 360-MHz TIADC system with an input signal fin of 110 MHz. The FPGA verification results show that after calibration and decimation, the spurious-free dynamic range (SFDR) and signal-to-noise distortion ratio (SNDR) improve by about 40 dB and 30 dB, respectively.

An 84-dB-SNDR Low-OSR Fourth-Order Noise-Shaping SAR With an FIA-Assisted EF-CRFF Structure and Noise-Mitigated Push-Pull Buffer-in-Loop Technique

To design a low-oversampled high-resolution noise-shaping successive approximation register (NS-SAR) analog-to-digital converters (ADCs), two main bottlenecks need to be addressed. One is to implement high-order optimized NS with simple and low-power hardware that maximally preserves a SAR’s efficient nature, and the other is to alleviate the sampling noise and input driving burden. This article presents a fourth-order NS-SAR ADC that synergistically addresses both challenges. It proposes an innovative error feedback-cascaded resonator feed-forward (EF-CRFF) structure and a noise-mitigated buffer-in-loop (BIL) technique. The former balances the robustness and energy efficiency by combining the merits of EF and CRFF structures, while the latter ensures the ADC to be low noise and easy-to-drive simultaneously. Prototyped in 65-nm CMOS technology, this work achieves 84.1-dB signal-to-noise-distortion ratio (SNDR) with 500-kHz bandwidth (BW) under a small OSR of 5. The prototype consumes 133.8- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> power under 1.2-V supply (including the power of in-loop buffer under 2-V supply), leading to a 180-dB Schreier figure of merit (FoM).

A 12bit 250 MS/s 5.43fJ/conversion-step SAR ADC with adaptive asynchronous logic in 28 nm CMOS

A 12-bit 250-MS/s adaptive asynchronous successive approximation registers analog-to-digital converter (SAR ADC) with a Non-binary segmented split capacitor array is proposed. The Non-binary bridge split capacitor array leads to much larger units with reduced total capacitance and allows for reducing digital-to-analog converter (DAC) settling time and power consumption. The reset time of the comparator is automatically and precisely adjusted according to the settling time required by each capacitor of the non-binary capacitor array, which accelerates the ADC quantization. With the proposed adaptive asynchronous logic (AAL), the settling time utilization will reach 98.6% and the overall ADC's speed can be increased by 30%. The circuit was designed in 28 nm CMOS technology. The mismatch of the capacitor is calibrated by the Least Mean Square (LMS) background calibration for high speed and low power consumption. Based on post-layout simulations, the ADC achieves a signal-to-noise distortion ratio (SNDR) of 67.92 dB at 250 MS/s sampling rate and consumes 2.76 mW, resulting in a figure of merit of 5.43fJ/conversion-step. The ADC core occupies an active area of only 100 μm × 350 μm.

A 4th-Order Continuous-Time Delta-Sigma Modulator With Hybrid Noise-Coupling

A hybrid noise-coupling (HNC) technique is proposed to mitigate the issues with a digital noise-coupling (DNC) structure. In the proposed technique, the unwanted quantization noise that is generated from the noise-coupling analog-to-digital converter (ADC) is injected into the input of the quantizer with one-clock cycle delay, thus increasing the order of noise-shaping of this error. Behavioral simulation shows that the HNC is highly robust against gain variation. The proposed fourth-order continuous-time (CT) delta-sigma modulator (DSM) with HNC scheme was designed in a 28-nm CMOS technology with a core size of 0.3mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . With an oversampling ratio (OSR) of 32, the proposed design achieves a signal-to-noise-distortion ratio (SNDR) of 97.20-dB at a signal bandwidth of 15.625-kHz, which has a 7-dB improvement in comparison to DNC only without introducing significant hardware complexity.

An analog‐to‐digital converter calibration algorithm with clock jitter compensation based on bidirectional long‐short‐time‐memory

This letter proposes a bidirectional long-short-time-memory (bi-LSTM)-based analog-to-digital converter (ADC) background calibration method with a clock jitter compensation function. Different from traditional calibration algorithms, the proposed algorithm utilizes the sequence property of the signal by introducing an LSTM network. The network contains three parts, including a linear layer for input encoding, a refine layer for sequence processing, and a linear layer for output decoding. Two ADCs are used to train the network, one of which is the target to be calibrated, that is, a high-speed high-resolution ADC, and the other is a low-speed ultra-high-resolution ADC producing the ideal signal. After the training stage, the network can be used as a postprocessor for the target ADC to compensate for the systemic errors and clock jitter, simultaneously. In the experiments, the proposed method is used to calibrate an ADC12D1600RFIUT, realizing the improvement of signal-to-noise distortion ratio (SNDR) from 43.41 to 66.82 dB and SFDR from 56.95 to 98.93 dB.

SAR ADC for a Multimode Radar Transceiver with Offset Calibration

In this paper, we design a successive approximation register (SAR) analog-to-digital converter (ADC) suitable for multimode radar transceivers. For multimode radars, the sampling rate required by ADC varies according to the continuous wave (CW) or frequency modulated continuous wave (FMCW) used for operation. Therefore, depending on which waveform is used, the input is designed to enter two paths. For path 1, we obtained 9.23 bits of effective number of bits (ENOB), 57.35 dB of signal-to-noise distortion ratio (SNDR), and 64.62 dB of spurious free dynamic range (SFDR), and the power consumption was 0.3481 mW, resulting in a figure of merit (FOM) of 28.9 fJ/Conv-Step. On path 2, we obtained an 8.97 bit of ENOB, 55.76 dB of SNDR, and 60.53 dB of SFDR, and the power consumption was 1.72 μW, resulting in a FOM of 34.2 fJ/Conv-Step. Further, a circuit was constructed to reduce the offset of the comparator. As a result of 100 Monte Carlo simulations, the offset was reduced from -46 mV/+50 mV to -4 mV/+4 mV when the worst case was considered.

All-digital calibration algorithm based on channel multiplexing for TI-ADCs

An adaptively calibration structure featured by channel multiplexing that can simultaneously calibrate the offset, gain, and timing mismatch errors existing in TI-ADC (Time-Interleaved ADC) channels in pure digital domain is proposed, which focuses on the problem of limited input signal bandwidth and high calibration hardware overhead. In error compensation aspect, these three mismatch errors are compensated simultaneously by adaptive method. The gain mismatch compensation employed here can help to overcome the deviation that would exist when the first-order Taylor compensation was employed alone for the timing mismatch, which can significantly improve the calibration effect in high-frequency band instead of employing complex high-order Taylor compensation structure. The total calibration algorithm is implemented using FPGA. For the 4-channel, 1 GS/s and 14-bit TI-ADC, the signal-to-noise distortion ratio (SNDR) of the system is increased from 26.19 dB to 84.37 dB, and the spurious free dynamic range (SFDR) is increased from 29.35 dB to 98.49 dB when the input signal normalized frequency f in / f s is 0.975.