Signal-to-noise Distortion Ratio Research Articles

A 12-bit 40 MS/s pipelined ADC with over 80 dB SFDR

This paper describes a 12-bit 40 MS/s calibration-free pipelined analog-to-digital converter (ADC), which is optimized for high spurious free dynamic range (SFDR) performance and low power dissipation. With a 4.9 MHz sine wave input, the prototype ADC implemented in a 0.18-μm 1P6M CMOS process shows measured differential nonlinearity and integral nonlinearity within 0.78 and 1.32 least significant bits at the 12-bit level without any trimming or calibration. The ADC, with a total die area of 3.1 × 2.1 mm2, demonstrates a maximum signal-to-noise distortion ratio (SNDR) and SFDR of 66.32 and 83.38 dB, respectively, at a 4.9 MHz analog input and a power consumption of 102 mW from a 1.8 V supply.

The design and optimization methodology of a low-distortion sub-[formula omitted] sample-and-hold stage for weak bio-currents

Current sample-and-hold (SHI) stage is important for reducing the signal distortion of bio-medical current detectors. Previous SHIs achieve high linearity only with high power consumption. This paper introduces a low-distortion switched-current (SI) sample-and-hold stage for high-performance current sampling of weak currents, by applying constant charge injection on a weakly inverted MOS transistor. The paper also introduces a methodology to design and optimize the SHI for a target signal-to-noise-distortion ratio (SNDR). A sample SHI is designed according to the methodology in a 0.35μm CMOS process. Silicon measurements verify that the fabricated SHI meets the design targets, and can achieve above 58dB SNDR and above 68dB spurious-free dynamic range (SFDR) at the sampling rate of 2kS/s for a 100nA input current up to 1kHz. The power consumption of the SHI is only 0.7μW.

An Enhanced Dual-Path .DELTA..SIGMA. A/D Converter

This paper presents an enhanced dual-path delta-sigma analog-to-digital converter. Compared with other architectures, the enhanced architecture increases the noise shaping order without any instability problems and displays analog complexity equivalent to the multi-stage noise shaping architecture. Our delta-sigma converter is based on this new architecture. It employs not only doubly-differential structure to reduce common-mode errors in the system-level but also delayed-feed-in structure to mitigate the timing constraint of the feedback signal. Regarding the circuit implementation, the first-order enhancement of the quantization noise shaping is achieved via the use of a switched capacitor circuit technique. The circuit is incorporated into the active adder in a low-distortion structure. The supporting clock generation circuit that provides additional phases of clocks with the enhancement block is also implemented in the CMOS logic gates. A digital dynamic element matching circuit (i.e., segmented data-weighted-average circuit) is designed to reduce mismatch errors caused by the feedback DAC of modulator. A test chip, fabricated in a 0.18-μm CMOS process, provides a signal-to-noise+distortion ratio (SNDR) of 75-dB for a 1.0-MHz signal bandwidth clocked at 40-MHz. The 2nd harmonic is ―101 dB and the 3rd harmonic is ―94 dB when a ―4.5-dB 100-kHz input signal is applied.

Low-Power and Wide-Bandwidth Cyclic ADC With Capacitor and Opamp Reuse Techniques for CMOS Image Sensor Application

In this paper, a power-efficient programmable gain amplifier (PGA) and a cyclic analog-to-digital converter (ADC) are developed for a satellite CMOS image sensor system. The cyclic ADC employs capacitor and opamp reuse techniques to reduce power consumption and occupied silicon area. Moreover, a power-efficient and wide-bandwidth telescopic cascode gain boosting amplifier with capacitive level shifters is adopted to decrease its power consumption further. According to the system specification, a 10-bit, 14-MS/s cyclic ADC with the front-end PGA circuit is implemented in the TSMC 0.18- ?m triple-well 1P3M CMOS image sensor (CIS) process. The proposed cyclic ADC achieves a spurious free dynamic range (SFDR) of 65.1 dB and a signal-to-noise distortion ratio (SNDR) of 52.44 dB with 5-MHz input frequency at 14 MS/s. The power consumption of the cyclic ADC and PGA from a 3.3 V supply are 15.84 mW and 5.78 mW, respectively. The total core area is 0.381 mm2 .

Bandpass Sigma–Delta Modulator Employing SAW Resonator as Loop Filter

Continuous-time bandpass (BP) sigma-delta modulators (SigmaDeltaMs) employing surface acoustic wave (SAW) resonators as loop filters are presented. Compared with the loop filters realized with Gm-C and LC resonators, the SAW resonator has the advantage of high-Q factor, wide resonant frequency range and accurate resonant frequency without the need for automatic tuning. With the proposed anti-resonance cancellation and loop filter phase compensation techniques, a second- and a fourth-order BP SigmaDeltaMs are demonstrated in a 0.35-mum CMOS technology. Both modulators are tested with 47.3-MHz off-chip SAW resonators. The second-order modulator attains a dynamic range of 57 dB and peak signal-to-noise distortion ratio (SNDR) of 54 dB and the fourth-order one achieves a dynamic range of 69 dB and peak SNDR of 66 dB, both in a 200-kHz signal bandwidth. The fourth-order modulator is also measured in a 3.84-MHz signal bandwidth and achieves a dynamic range of 52.5 dB and peak SNDR of 50 dB, an effective 8-bit resolution

An 11b 70-MHz 1.2-mm/sup 2/ 49-mW 0.18-/spl mu/m CMOS ADC with on-chip current/voltage references

This work proposes an 11b 70-MHz CMOS pipelined analog-digital converter (ADC) as one of core circuit blocks for very high speed digital subscriber line system applications. The proposed ADC for the internal use has the strictly limited number of externally connected I/O pins while the ADC employs on-chip CMOS current/voltage references and a merged-capacitor switching technique to improve ADC performances. The ADC implemented in a 0.18-/spl mu/m 1P4M CMOS technology shows the maximum signal-to-noise distortion ratio (SNDR) of 60 dB at 70 MSample/s. The ADC maintains the SNDR of 58 dB and the spurious-free dynamic resistance of 68 dB for input frequencies up to the Nyquist rate at 60 MSample/s. The measured differential and integral nonlinearities of the ADC are within /spl plusmn/0.63 and /spl plusmn/1.21 LSB, respectively. The active chip area is 1.2 mm/sup 2/ and the ADC consumes 49 mW at 70 MSample/s at 1.8 V.

A 900 mV 66 W Sigma-Delta Modulator Dedicated to Implantable Sensors

In this paper, a low-voltage low-power sigma-delta modulator dedicated to implantable sensing devices is presented. This second-order single-loop sigma-delta modulator is implemented with half-delay integrators. These integrators are based on new fully-differential CMOS class AB switched-Operational Transconductance Amplifier (switched-OTA). An on-chip voltage doubler is introduced to locally boost a supply voltage at the input stage of a conventional OTA in order to allow rail-to-rail signal swing. Experimental results of the modulator fabricated in CMOS 0.18 μm technology confirm its expected features of a peak signal-to-noise ratio (SNR) of 72 dB, a signal-to-noise distortion ratio (SNDR) of 62 dB in a 5 kHz signal bandwidth, and a power consumption lower than 66 μW with a 900 mV voltage supply.

A 1-MHz-bandwidth second-order continuous-time quadrature bandpass sigma-delta modulator for low-IF radio receivers

This paper presents a quadrature bandpass /spl Sigma//spl Delta/ modulator with continuous-time architecture. Due to the continuous-time architecture and the inherent anti-aliasing filter, the proposed /spl Sigma//spl Delta/ modulator needs no additional anti-aliasing filter in front of the modulator in contrast to quadrature bandpass /spl Sigma//spl Delta/ modulators with switched-capacitor architectures. The second-order /spl Sigma//spl Delta/ modulator digitizes complex analog I/Q input signals at 1-MHz intermediate frequency and operates within a clock frequency range of 25-100 MHz. The modulator chip achieves a peak signal-to-noise-distortion ratio (SNDR) of 56.7 dB and a dynamic range of 63.8 dB within a 1-MHz signal bandwidth and at a clock frequency of 100 MHz. Furthermore, it provides an image rejection of at least 40 dB. The 0.65-/spl mu/m BiCMOS chip consumes 21.8 mW at 2.7-V supply voltage.

14-bit 2.2-MS/s sigma-delta ADC's

This paper presents the design and test results of a fourth-order and sixth-order 14-bit 2.2-MS/s sigma-delta analog-to-digital converter (ADC). The analog modulator and digital decimator sections were implemented in a 0.35 /spl mu/m CMOS double-poly triple-level metal 3.3-V process. The design objective for these ADC's was to achieve 85 dB signal-to-noise distortion ratio (SNDR) with less than 200 mW power dissipation. Both modulators employ a cascade sigma-delta topology. The fourth-order modulator consists of two cascaded second-order stages which include 1-bit and 5-bit quantizers, respectively. The sixth-order modulator has a 2-2-2 cascade structure and 1-bit quantizer at the end of each stage. An oversampling ratio of 24 was selected to give the best SNDR and power consumption with realizable gain-matching requirements between the analog and digital sections.

Design techniques for high-resolution current-mode sigma-delta modulators

This paper describes techniques for the design of high-resolution oversampling analog-to-digital converters based on current memories. A key point is the reduction of nonlinearities, in particular those introduced by the current switches. A current-memory cell with very high precision and linearity has been designed and used in an experimental third-order /spl Sigma/-/spl delta/ modulator in a 0.8-/spl mu/m digital CMOS process. A linearity of better than 14 b and a maximum signal-to-noise+distortion ratio (SNDR) of 80 dB has been measured for an oversampling ratio (OSR) of 64.

A third-order sigma-delta modulator with extended dynamic range

Oversampling modulators based on high-order sigma-delta modulation provide an effective means of achieving high-resolution analog-to-digital conversion in VLSI technology. Because high-order noise shaping greatly reduces the quantization noise in the signal band, the dynamic range of these modulators tends to be bounded by the thermal noise of the input stage and the maximum voltage swing in the signal path. This paper introduces a third-order cascaded sigma-delta modulator that uses a modified cascaded architecture and reduced gain in the first integrator to increase the dynamic range. An experimental modulator fabricated in a 1-/spl mu/m CMOS technology attains a resolution of 17 b for a 25-kHz signal bandwidth while operating from a single 5-V supply. With an oversampling ratio of 128 and a clock frequency of 6.4 MHz, the modulator achieves a 104-dB dynamic range and a peak signal-to-noise+distortion ratio (SNDR) of 98 dB. As indicated by both measurements and simulations, the cascaded architecture also greatly reduces the discrete noise peaks that can be present in a single-stage architecture. >