Development of a low-power SAR ADC for analog front-end readout circuit of hydrophones

Abstract

A low-power 16 bit 250KSa/s successive approximation analog-to-digital converter (SAR ADC) is designed. The capacitor array consists of a 2-segment sub-capacitor array and high sampling makes the coupling capacitance a unit capacitance, solving the problem of fractional capacitance mismatch. The power consumption is reduced by introducing a common-mode voltage during the switching process of the capacitor array. The circuit uses a 4-stage pre-amplifier and adds a dynamically latched comparator using output misalignment calibration to ensure high accuracy resolution. Simulated in DB Hitek 0.18 μm process, the Fast Fourier Transform(FFT) simulation results for 4096 points show that the signal-to-noise distortion ratio (SNDR) of the ADC can reach 90.2 dB and the effective number of bits (ENOB) can reach 14.69 bit. The average power consumption is 2.507mW at a supply voltage of 5 V, and this holds significant significance for the long-term deep-sea detection capabilities of sonar systems.