Sidewall Process Research Articles

Nitride spacer aided 0.15 μm AlGaN/GaN HEMT fabrication with optimized gate patterning process

I-line stepper is widely used in large scale device manufacturing with limited achievable critical dimension by itself. With the aid of the spacer sidewall, the critical dimension can be further shrunk down. Spacer sidewall aided process necessitates an additional deposition-etching process, which inevitably results in process related damage under the gate. This paper proposes an optimized spacer sidewall aided gate patterning procedure for 0.15 μm GaN High Electron Mobility Transistors (HEMTs) fabrication. The process is proved to be effective in improving device performance compared to conventional sidewall process by keeping first Si-rich SiN passivation layer integrity at the gate edge. Interface trap density (Dit) and mobility were extracted for both conventional sidewall process and the optimized one with different passivation layers at the gate edge, demonstrating a lower Dit and higher mobility using the optimized process with enhanced device performances, such as higher current, breakdown voltage, and stress state characteristics, compared to the conventional process, which is promising for mass production of 0.15 μm GaN HEMTs.

Characterization of a self‐aligned RTD using a SiNx sidewall process for high‐speed applications

AbstractIn this article, an InP‐based self‐aligned resonant‐tunneling‐diode (RTD) using a SiNX sidewall process has been fabricated and characterized for high‐speed microwave applications. A plasma‐enhanced dry‐etch technique has been used to form a vertical emitter mesa. The measured peak currents are almost constant at a peak voltage due to negligible thermionic emission in a wide temperature range up to 125°C. The extracted series resistance of the fabricated self‐aligned RTD is 14.5 Ω, which is reduced by 27% compared with that of the nonself‐aligned RTD by reducing the spacing between emitter mesa and collector metal. To the best of authors’ knowledge, this is the first attempt to characterize a self‐aligned RTD using the dry‐etched mesa and the SiNX sidewall structure.

Indium Phosphide Heterobipolar Transistor Technology Beyond 1-THz Bandwidth

Recent improvements in the fabrication technology of InGaAs/InP heterobipolar transistors have enabled highly scaled transistors with power gain bandwidths above 1 THz. Limitations of the conventional fabrication process that reduce RF bandwidth have been identified and mitigated, among which are high resistivity base ohmic contacts, resistive base electrodes, excessive emitter end undercut, and insufficient undercut of large-diameter base posts. A novel two-step deposition process for self-aligned metallization of sub-20-nm bases has been developed and demonstrated. In the first step, a metal stack is directly evaporated onto the base semiconductor without any lithographic processing so as to minimize contamination from resist/developer chemistry. The composite metal stack exploits an ultrathin layer of platinum that controllably reacts with base, yielding low contact resistance, as well as a thick refractory diffusion barrier, which permits stable operation at high current densities and elevated temperatures. Further reduction of overall base access resistance is achieved by passivating base and emitter semiconductor surfaces in a combined atomic layer deposition Al2O3 and plasma-enchanced chemical vapor depositon SiNx sidewall process. This technology enables the deposition of low-sheet-resistivity base electrodes, further improving overall base access resistance and $f_{\textrm {max}}$ bandwidth. Additional process enhancements include the significant reduction of device parasitics by scaling base posts and controlling emitter end and base postundercut.

Scaling Down Characteristics of Vertical Channel Phase Change Random Access Memory (VPCRAM)

In this paper, scaling down characteristics of vertical channel phase random access memory are investigated with device simulator and finite element analysis simulator. Electrical properties of select transistor are obtained by device simulator and those of phase change material are obtained by finite element analysis simulator. From the fusion of both data, scaling properties of vertical channel phase change random access memory (VPCRAM) are considered with ITRS roadmap. Simulation of set reset current are carried out to analyze the feasibility of scaling down and compared with values in ITRS roadmap. Simulation results show that width and length ratio of the phase change material (PCM) is key parameter of scaling down in VPCRAM. Thermal simulation results provide the design guideline of VPCRAM. Optimization of phase change material in VPCRAM can be achieved by oxide sidewall process optimization.

Modeling the VAPEX and SAGD Side Wall Process with a Wax Heating Experiment

Physical modeling of a difficult process can give useful insights on how to capture the correct physics so as to build a computer model of the process. In this article it is suggested that a candle wax experiment can simulate crude oil drainage by VAPEX (solvent application) or SAGD (heat application) along the heavy oil interface. The experimental set-up, some initial data, and some suggestions for expansion of the experiment are presented here.

Effect of Scaling $\hbox{WO}_{x}$-Based RRAMs on Their Resistive Switching Characteristics

We investigated the effect of scaling down the device area of WOx resistive random-access memory (RRAM) devices on their switching characteristics. Device dimensions were successfully scaled down to 50 nm using a via-hole structure with additional Al2O3 sidewall process. As compared to the microscale devices, the nanoscale devices exhibited a distinct switching mechanism and better memory performance, such as improved switching uniformity, larger memory window, and stable endurance characteristics for up to 107 cycles. This improvement can be explained by a uniform interfacial switching mechanism in nanoscale device; this is in contrast with the defect-induced filamentary switching mechanism observed in microscale devices. In this way, the intrinsic switching properties of RRAMs were obtained by scaling down of the device area, indicating that RRAMs hold considerable promise for future applications.

Development of Carbon Rich Spin-on Sidewall Material

Sidewall process has been proposed as one of the acceptable self aligned double patterning technologies (SADPT). In this study, carbon rich spin-on sidewall (SoS) materials have been investigated. And the possibility of applying them in novel double patterning process has been explored. This process has some merits in terms of cost reduction and throughput compared with CVD sidewall process. And it is easy to apply this material for conventional litho film stacks. However, how to control critical dimension has been one of the key tasks to be dissolved. And, several issues including etch resistance and solubility must be addressed. Thus, carbon rich polymer having alkali soluble unit and cross-linking unit was chosen for this purpose. The sidewall width is controlled by the cross-link reaction using a concept similar to negative-tone photoresist. The driving force of cross-linking reaction is acid diffusion from the resist. As a result, it was confirmed that SoS pattern was formed and the critical dimension of the sidewall can be controlled by adjusting the amount of acid amplifier. By using SoS materials we successfully converted 1:3 L/S pattern to dense pattern.

A Cost Effective Spin on Sidewall Material Alternative to the CVD Sidewall Process

193nm immersion and Hyper NA lithography are used at 45nm and beyond. The next generation of lithography will use a new technology such as Double Pattering, EUV or EB. Double patterning is one of the currently acceptable technologies. Three common double pattern techniques are Litho-Etch-Litho-Etch (LELE), freezing, and sidewall (spacer) process. From a technical standpoint LELE is a very promising process, except for the second litho alignment. However, the cost of ownership will be very high because LELE will cost about twice as much as the current single litho patterning process. In order to build up a suitable double patterning technique, many device makers are developing unique processes. Two of these processes are freezing and sidewall. Flash memory makers are diligently investigating the sidewall process by CVD. This is because of the lack of a second litho alignment step, even with its high cost. The high cost of the CVD process can be reduced if a spin on material is used. One of the goals of this paper is to reduce the cost of ownership by using spin on coatings for the sidewall process. Currently we are investigating this approach to control the sidewall width, profile and other properties.

Monitoring of test gullies development from the Moldavian Tableland in 1986 - 2008 period

In a study area in Romania covering about 25,000 km 2 over 9000 gullies were mapped. The areal distribution of the gullies indicated some areas where a higher density occurs. These areas are dominated by hillslope orientation towards the northwest and, respectively, the southeast, slope inclination between 20 to 30 m/100 m, slope length between 300 and 500 m and by a dominantly sandy lithology. Detailed field surveys were made of 17 gullies. Each gully was marked with a network of stakes to show the location of cross sections. The distances between cross sections were around 3-4 times the gully width. Topographical maps at scales of 1:200 to 1:500 were made for gully geomorphological surveys. In 2007-2008 we were interested in the evolution of the test gullies and if the evolution pattern we had proposed in 1999 was verified by the new measurements. In this work we will focus on the monitoring methods of the test gullies from our work database. Finally, we intend to present the calibrated pattern of the gully evolution. The distribution of gullies indicates that the highest gully density reflects hillslope orientation, inclination and length, and a sandy lithology. In Moldavia the average number of gullies per kms is between 2 to 4, with a maximum of 20 gullies per kms; average density is between 0.1 to 1 km per kms, with a maximum length value of over 3 km per km. Gully number and density per surface unit are considered as classification criteria of gully erosion. The areas with the highest susceptibility of gully initiation in Moldavia are at the intersection of following factors: hillslope orientation towards NW and SE, respectively (hillslopes of consequent valleys), slope inclination between 20 to 30%, slope length between 300 and 500 m and a dominantly sandy lithology. These areas have a high density of points. Detailed investigations on 17 gullies sampled from the different areas of Moldavia between the Siret and Prut rivers in the period 1986-2008 show that some of the properties of gully geometry favour using discriminating factors to produce a diagnosis and a possible assessment of geomorphic development. Factor identification can be used to identify the most important combinations of geomorphic processes in gully development. The surface deposits of gullies studied vary from silty-clays in the northern half of the territory, to silts in the middle to southern area and sands in the southern end of the region. For the cases studied, the sidewall processes contribute 1-5 times more to the gully evolution than the incision processes. The nature of the processes in a gully may be inferred by the grain size analysis of the surface material. The rate of gully head cutting is over 1.5 m/year for gullies cut in sandy deposits and under 1 m/year for the gullies cut in marls and clays. A model of gully development is proposed which shows an accelerated rate of gully development immediately downstream after their initiation and a reduced and even cessation of advance on attaining an equilibrium length.

InP Bipolar ICs: Scaling Roadmaps, Frequency Limits, Manufacturable Technologies

Indium phosphide heterojunction bipolar transistors (HBTs) find applications in very wide-band digital and mixed-signal integrated circuits (ICs). Devices fabricated in high-yield process flows at 500 nm feature size obtain 450 GHz cutoff frequencies and 5 V breakdown and enable high yield fabrication of integrated circuits having more than 3000 transistors. Laboratory devices at 250 nm feature size obtain 755 GHz . We describe device and circuit bandwidth limits associated with HBTs, develop scaling roadmaps for HBTs having lithographic minimum feature sizes between 512 and 64 nm, and identify key technological challenges in realizing 480-GHz digital ICs and 1000-GHz amplifiers. Key features of manufacturable self-aligned dielectric sidewall processes are described in detail.

Improvement of Mesa-Sidewall Leakage Current Using Benzocyclobuten Sidewall Process in InGaAs/InP MSM Photodetector

In recent decades, metal-semiconductor-metal (MSM) photodetector for optical fiber communication applications have been studied extensively. The dark current in MSM PD is an important parameter that can be reduced by schottky barrier enhancement and fabrication process. By employing a benzocyclobuten (BCB) sidewall passivation process, the leakage issue between Schottky metal fingers and mesa sidewalls can be avoided. Moreover, the parasitic capacitance can also be decreased due to the low dielectric constant of BCB. The BCB passivation process decreases the dark current density from 11 nA/µm2 to 5.7 pA/µm2.

Twin SONOS Memory With 30-nm Storage Nodes Under a Merged Gate Fabricated With Inverted Sidewall and Damascene Process

By manipulating the charge profile through the inverted sidewall patterning on the channel, stable 2-bit operation in silicon-oxide-nitride-oxide-silicon (SONOS) Flash memory with sub-90-nm gate length can be achieved. The fabricated memory cell has about 30-nm twin Oxide-Nitride-Oxide-Silicon physically separated by the inverted sidewall patterning method under the same control gate based on damascene gate process. Comparing with a conventional single SONOS memory (SSM), this novel twin SONOS memory cell can maintain the better control of trapped charge distribution due to the strong diffusion barrier of charges. As a result, better endurance, retention, and erase speed than SSM can be obtained in the short (sub-100-nm) gate length devices.

30 nm Triple-Gate In0.7GaAs HEMTs Fabricated by Damage-Free SiO2/SiNx Sidewall Process and BCB Planarization

A 30 nm In0.7GaAs high electron mobility transistor (HEMT) with triple-gate has been successfully fabricated using the SiO2/SiNx sidewall process and BCB planarization. The sidewall gate process was used to obtain finer lines, and the width of the initial line could be lessened to half by this process. To fill the Schottky metal effectively to a narrow gate line after applying the developed sidewall process, the sputtered tungsten (W) metal was utilized instead of conventional e-beam evaporated metal. To reduce the parasitic capacitance through dielectric layers and the gate metal resistance (Rg), the etched-back BCB with a low dielectric constant was used as the supporting layer of a wide gate head, which also offered extremely low Rg of 1.7 Ohm for a total gate width (Wg) of 2×100 µm. The fabricated 30 nm In0.7GaAs HEMTs showed Vth of -0.4 V, Gm,max of 1.7 S/mm, and fT of 421 GHz. These results indicate that InGaAs nano-HEMT with excellent device performance could be successfully fabricated through a reproducible and damage-free sidewall process without the aid of state-of-the-art lithography equipment. We also believe that the developed process will be directly applicable to the fabrication of deep sub-50 nm InGaAs HEMTs if the initial line length can be reduced to below 50 nm order.

Analog experiments on melting and contamination at the roof and walls of magma chambers

A series of analogue laboratory experiments were carried out to model melting and mixing processes occurring at the roof and sides of a magma chamber when hot, dense mantle-derived magmas are emplaced in the deep crust. The experiments investigated the influence of a viscosity contrast between crustal melts and input magma, the presence of crystals in the input magma, and roof geometry. The crust was modelled by aqueous ice or a cold, low-melting point wax, arranged as a flat roof or in an upside-down U. The input magma was modelled by a hot, dense aqueous solution of NaNO 3 or FeSO 4, which was injected into the cavity between the walls. The experiments revealed the potentially important role that side-wall processes may have in crustal melting and mantle magma contamination in this environment. The walls melted back much faster than the roof and the melts from the opposite walls ponded next to each other under the roof and mixed with each other only in the central region. When the input solution was able to crystallise, it did so preferentially in the active side-wall boundary layers. The tiny, dense crystals, which were dragged up in the melt boundary layer and then dropped into the interior fluid, enhanced hybridisation of the melt and contamination of the input fluid and, through their influence on the boundary layer structure, reduced the melting rate.

Assessment of sidewall erosion in large gullies using multi-temporal DEMs and logistic regression analysis

Although in the last decades gully erosion has been a thriving research field, few studies have specifically addressed the contribution and location of sidewall erosion processes in gullies. In this paper, sidewall erosion in some large gullies in a Mediterranean area (Anoia-Penedès, NE Spain) is mapped and assessed for two time intervals (1975–1995 and 1995–2002), using detailed digital elevation models derived from aerial photographs at a scale of 1:5000 to 1:7000. Logistic regression analysis is applied to compute the probability of occurrence of gully sidewall erosion from terrain variables. The results confirm the complex nature of sidewall processes, whose intensity is most probably related to rainfall characteristics. Prolonged wet soil conditions in the period 1995–2002, together with the large and high-intensity rainfall of an extreme event occurred on 10th June 2000, help to explain the different sediment production rates: 16±0.4 Mg ha −1 year −1 in 1975–1995 and 83±6.3 Mg ha −1 year −1 in 1995–2002. The logistic regression analysis revealed that gully-wall slope angle was the main factor controlling gully sidewall failure. In gully walls with high slope angles, tension crack development is the main process promoting wall collapse. The application of the logistic regression model showed a high overall accuracy (87%) but over 50% of commission and omission errors for the class of interest (sidewall erosion), in agreement with the variance explained by the model.

Fabrication of single-electron tunneling transistors with an electrically formed Coulomb island in a silicon-on-insulator nanowire

For the purpose of controllable characteristics, silicon single-electron tunneling transistors with an electrically formed Coulomb island are proposed and fabricated on the basis of the sidewall process technique. The fabricated devices are based on a silicon-on-insulator (SOI) metal–oxide–semiconductor (MOS) field effect transistor with the depletion gate. The key fabrication technique consists of two sidewall process techniques. One is the patterning of a uniform SOI nanowire, and the other is the formation of n-doped polysilicon sidewall depletion gates. While the width of a Coulomb island is determined by the width of a SOI nanowire, its length is defined by the separation between two sidewall depletion gates which are formed by a conventional lithographic process combined with the second sidewall process. These sidewall techniques combine the conventional lithography and process technology, and guarantee the compatibility with complementary MOS process technology. Moreover, critical dimension depends not on the lithographical limit but on the controllability of chemical vapor deposition and reactive-ion etching. Very uniform weakly p-doped SOI nanowire defined by the sidewall technique effectively suppresses unintentional tunnel junctions formed by the fluctuation of the geometry or dopant in SOI nanowire, and the Coulomb island size dependence of the device characteristics confirms the good controllability. A voltage gain larger than one and the controllability of Coulomb oscillation peak position are also successfully demonstrated, which are essential conditions for the integration of a single-electron tunneling transistor circuit. Further miniaturization and optimization of the proposed device will make room temperature designable single-electron tunneling transistors possible in the foreseeable future.

The Effects of Plasma Induced Damage on The Channel Layers of Ion Implanted GaAs MESFETs during Reactive Ion Etching(RIE) and Plasma Ashing Processes

AbstractThe gate length of GaAs MESFETs is required to be shorter for higher microwave frequency applications. The side-wall process using silicon nitride is one of the effective processes to fabricate short gate length GaAs MESFETs. The side-wall process consists of deposition and anisotropic etching of silicon nitride and delivers plasma induced damages on the channel layers of the devices. In this study, the effects of plasma induced damage on the channel layers of ion implanted GaAs MESFETs during reactive ion etching and plasma ashing processes have been investigated. The plasma induced damage was characterized by sheet resistance measurement, Xray photoelectron spectroscopy(XPS) and auger electron spectroscopy(AES) of different etched surfaces, compared with a chemically wet-etched reference surface. Also the effect of the plasma induced damage on the device performance was investigated. As a result, plasma ashing can deteriorate the plasma-induced damage by RIE.

A method for dendrochronological assessment of medium-term gully erosion rates

A method based on dendrochronology to estimate gully erosion rates was developed as an alternative of traditional methods for assessing medium-term gully retreat rates, such as field monitoring of headcuts or aerial-photo interpretation of gully retreat. The method makes use of trees or parts of a tree affected by gully erosion revealing information on the history of the erosion process by datable deviations of their normal growth pattern, hence defined as ‘datable objects’. These include roots exposed by erosion; browsing scars made by ungulates on exposed roots or on above-ground parts of fallen trees; exposed and dead root ends; root suckers; stems, branches and leading shoots of fallen trees; and a sequence of trees within a gully. The method is based on the differentiation between three main conditions depending on the relation between the dynamics of the datable object (part of the tree) and the development of the gully. The first condition implies that the datable object was created before erosion of the gully volume to be dated, e.g. exposed tree roots. According to the second condition, the datable object developed as an immediate consequence of the erosion event, e.g. growth reactions of a fallen tree. The third condition implies that the datable object was created some time after the erosion event took place, e.g. trees colonising the gully bed. Each principle has consequences for the accuracy and the correct interpretation of the estimated erosion rate, i.e. whether the true erosion rate is underestimated, exact or overestimated. In spite of methodological limitations and dendrochronological dating problems, the method was successfully applied in southeast Spain. Conservative estimations of gully-head retreat rate resulted in an average medium-term (3–46 years) value of 6 m 3 year −1 ( n=9). For gully sidewall processes, the average minimum erosion rate per unit sidewall length amounted 0.1 m 3 year −1 m −1 ( n=9). A strong correlation was found between the headcut retreat rate ( v m(ortho), m 3 year −1) and the drainage–basin area ( A, m 2) of the gullies, expressed by v m(ortho)=0.02 A 0.57 ( R 2=0.93, n=9). Comparing the findings from this study with those obtained by short-term headcut retreat monitoring suggests a high reliability of the estimated retreat rates, supporting the applicability of the developed dendrochronological method.

Increase of parasitic resistance in shallow p/sup +/ extension by SiN sidewall process and its improvement by Ge preamorphization for sub-0.25-μm pMOSFET's

Anomalously high parasitic resistance is observed when SiN gate sidewall spacer is incorporated into sub-0.25-/spl mu/m pMOSFET's. The parasitic resistance in p/sup +/ S/D extension region increases remarkably by decreasing BF/sub 2/ ion implantation energy to lower than 10 keV. It is confirmed that low activation efficiency of boron in p/sup +/ extension is the reason for such high parasitic resistance. The reduction of activation efficiency of boron may result from hydrogen passivation of boron acceptor; Fourier transform infrared absorption (FT-IR) measurement suggests that diffused hydrogen from SIN into p/sup +/ extension region forms the silicon-hydrogen-boron complex. It is also found that the activation efficiency of boron correlates well both with implantation energy of BF/sub 2/ and the amorphization rate of substrate. Therefore, in sub-0.25-/spl mu/m era, the extra amorphization step is essential not only to form a shallow junction but also to enhance boron activation. Germanium preamorphization implantation (Ge PAI) is hence applied to p/sup +/ extension of 0.15 /spl mu/m pMOSFET's. It is finally demonstrated that this Ge PAI process reduces the total parasitic resistance to improve the drain saturation current by up to 10%.

Facet Free Selective Silicon Epitaxy by Rapid Thermal Chemical Vapor Deposition

ABSTRACTA facet-free, selective epitaxy process has been identified using the SiH2CI2 /HCI/H2 chemistry in a commercially available, single-wafer epitaxy reactor. The pre-epitaxy bake required a minimum of 900°C in order to obtain a clean silicon surface with reasonable throughput while preserving the integrity of the shallow trench isolation structures. The epitaxy growth rate ranged from as low as 130Å/rnin at 825°C, 10 torr to as high as 1500 Å/min at 875°C and 70 torr while the deposition rate of polysilicon on polysilicon differed significantly: at 10 torr, the epitaxy growth rate is greater by as much as 50%, and at 70 torr the polysilicon deposition rate is greater by as much as 40%. The facet suppression depended heavily on two things: the undercut beneath the polysilicon gate sidewall insulator and the process pressure. The undercut is believed to be responsible for suppressing the initial stage of facet formation, most probably by completely eliminating lateral overgrowth of the crystal. The process conditions then enable continued facet suppression perhaps by restricting the silicon surface mobility. The sidewall structure and process conditions combine to make a reliably facet-free selective epitaxy process