Increase of parasitic resistance in shallow p/sup +/ extension by SiN sidewall process and its improvement by Ge preamorphization for sub-0.25-μm pMOSFET's

Abstract

Anomalously high parasitic resistance is observed when SiN gate sidewall spacer is incorporated into sub-0.25-/spl mu/m pMOSFET's. The parasitic resistance in p/sup +/ S/D extension region increases remarkably by decreasing BF/sub 2/ ion implantation energy to lower than 10 keV. It is confirmed that low activation efficiency of boron in p/sup +/ extension is the reason for such high parasitic resistance. The reduction of activation efficiency of boron may result from hydrogen passivation of boron acceptor; Fourier transform infrared absorption (FT-IR) measurement suggests that diffused hydrogen from SIN into p/sup +/ extension region forms the silicon-hydrogen-boron complex. It is also found that the activation efficiency of boron correlates well both with implantation energy of BF/sub 2/ and the amorphization rate of substrate. Therefore, in sub-0.25-/spl mu/m era, the extra amorphization step is essential not only to form a shallow junction but also to enhance boron activation. Germanium preamorphization implantation (Ge PAI) is hence applied to p/sup +/ extension of 0.15 /spl mu/m pMOSFET's. It is finally demonstrated that this Ge PAI process reduces the total parasitic resistance to improve the drain saturation current by up to 10%.