Abstract
A 30 nm In0.7GaAs high electron mobility transistor (HEMT) with triple-gate has been successfully fabricated using the SiO2/SiNx sidewall process and BCB planarization. The sidewall gate process was used to obtain finer lines, and the width of the initial line could be lessened to half by this process. To fill the Schottky metal effectively to a narrow gate line after applying the developed sidewall process, the sputtered tungsten (W) metal was utilized instead of conventional e-beam evaporated metal. To reduce the parasitic capacitance through dielectric layers and the gate metal resistance (Rg), the etched-back BCB with a low dielectric constant was used as the supporting layer of a wide gate head, which also offered extremely low Rg of 1.7 Ohm for a total gate width (Wg) of 2×100 µm. The fabricated 30 nm In0.7GaAs HEMTs showed Vth of -0.4 V, Gm,max of 1.7 S/mm, and fT of 421 GHz. These results indicate that InGaAs nano-HEMT with excellent device performance could be successfully fabricated through a reproducible and damage-free sidewall process without the aid of state-of-the-art lithography equipment. We also believe that the developed process will be directly applicable to the fabrication of deep sub-50 nm InGaAs HEMTs if the initial line length can be reduced to below 50 nm order.
Published Version
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
