SiC Wafers Research Articles

Local capacitance-voltage profiling and deep level transient spectroscopy of SiO2/SiC interfaces by scanning nonlinear dielectric microscopy

We extend our local capacitance-voltage profiling method for the real-space nanoscale investigation of the SiO2/SiC interface, which is still an issue in the application of SiC to power electronics devices. Our technique is based on time-resolved scanning nonlinear dielectric microscopy and can be used for collecting local capacitance-voltage and its voltage-derivative profiles at each measurement point. This technique can also be combined with local deep level transient spectroscopy for simultaneously imaging the spatial fluctuations of interface defect density in real-space. Here we use the proposed technique to measure SiC wafers with a thermal oxide layer and investigate the effect of interface nitridation. From the data volume obtained by our technique, various images are extracted and their correlation is analyzed to characterize and discuss the spatial fluctuations and hysteresis of the local capacitance-voltage profiles. As expected, the nitridation of the SiO2/SiC interface after thermal oxidation is effective for the reduction of hysteresis and fluctuations in local capacitance-voltage profiles. However, significant spatial fluctuations remain even after the nitridation treatment, which suggests the SiO2/SiC interface has intrinsic non-uniformity generating high surface potential fluctuations.

High−Performance 4H−SiC UV p−i−n Photodiode: Numerical Simulations and Experimental Results

In this work, the optical response of a high−performance 4H−SiC−based p−i−n ultraviolet (UV) photodiode was studied by means of an ad hoc numerical model. The spectral responsivity and the corresponding external photodiode quantum efficiency were calculated under different reverse biases, up to 60 V, and in the wavelength range from λ = 190 to 400 nm. The responsivity peak is R = 0.168 A/W at λ = 292 nm at 0 V and improves as bias increases, reaching R = 0.212 A/W at 60 V and λ = 298 nm. The external quantum efficiency is about 71% and 88%. The good quality of the simulation setup was confirmed by comparison with experimental measurements performed on a p−i−n device fabricated starting from a commercial 4H−SiC wafer. The developed numerical model, together with the material electrical and optical parameters used in our simulations, can be therefore explored for the design of more complex 4H−SiC−based solid−state electronic and optoelectronic devices.

Formation mechanism of horizontal-half-loop arrays and stacking fault expansion behavior in thick SiC epitaxial layers

The formation mechanism of half-loop arrays (HLAs) that form parallel (horizontal) to the step-flow direction in 120 μm thick 4H-silicon carbide (SiC) epitaxial layers was investigated using ultraviolet photoluminescence (UVPL) imaging and x-ray topography (XRT). The horizontal-HLAs are generated by the multiplication and glide of basal plane dislocation (BPD) loops that are created within the epitaxial layer. The BPD loops were initiated after ∼40–50 μm of growth from a small BPD segment, which glides toward the surface as well as the substrate interface. BPD multiplication occurs and several loops are generated. Some of these loops are terminated by the growth front and create HLAs due to the 4° offcut of the wafer. XRT images show that successive BPD loops interact with previously generated HLA segments. Successive loops also interact with the moving growth front and create new HLAs that are spatially displaced from the previous HLA segments. These appear as a string of horizontal-HLAs in the UVPL images. The expansion of stacking faults (SFs) from these horizontal-HLAs was investigated, and we show that they all lie on the same basal plane. The complex defect structure is created in the epitaxial layer from a single BPD loop but extends over a large (∼5 × 0.5 cm2) region of the SiC wafer during epitaxial growth. The high density of HLAs and BPDs would generate several SFs upon device operation leading to severe device degradation.

Identification of Polytype and Estimation of Carrier Concentration of Silicon Carbide Wafers by Analysis of Apparent Color using Image Processing Software

n-type SiC wafers with localized 4H, 6H, and 15 R polytype grains were photographed and their colors were analyzed to find correlations among polytypes, carrier concentration and apparent color. The SiC wafers were photographed and the color information of different colored regions from the photographs was extracted, both for RGB (red, green, and blue) and HSV (hue, saturation, and value) color space formats using image processing software (PicMan). Polytype and carrier concentration of n-type SiC wafers were identified from Raman spectra for correlation with the color analysis results. The carrier concentration of SiC wafers was estimated to be in the range of 2 × 1017 cm−3 to 1 × 1019 cm−3 from a line-shape analysis of measured Raman spectra. The color analysis revealed that there is very strong correlation between polytype and hue value. The carrier concentration strongly affects saturation and value of apparent color. SiC wafers with lower carrier concentration showed higher clarity (lower saturation (or colorless) and higher value (higher transparency)). As the carrier concentration is increased, the wafer becomes translucent (high saturation or colored) and dark or opaque (low value). The polytype and carrier concentration of SiC wafers can conveniently be estimated from their apparent color.

Measurement of Dislocation Density in SiC Wafers Using Production XRT

X-ray topography (XRT) presents itself as an attractive non-destructive method to replace industry-standard destructive KOH etching used to measure dislocation density. However, a production-line-compatible XRT has to employ a low scan speed in order to work well with automated image analysis, which makes it impractical for a high-volume manufacturing to scan an entire wafer. We introduce the “radial band” approach to sampling the entire wafer’s area with a single-pass 16 mm tall scan band. Such a band spans the entire range of radii and thus captures the typically strong radial dependence of dislocation density over the entire range, while mostly ignoring the typically weak angular dependence of dislocation density and averaging the inevitable noise over the 16 mm band height. The XRT scan time savings for this approach are roughly 15-fold and 20-fold for 150mm and 200mm wafers respectively.

Fabrication and Characterization of Epitaxial Graphene Field Effect Transistor Devices Based on a Monolithic Bottom Gate

Current electronics technology increasingly demands higher integration, flexibility, higher efficiency, and performance aspects such as compatibility with higher temperature operation of the semiconductor devices, which may find limitations when silicon is used. The superior intrinsic properties of SiC, eventually combined with the ability of growing monolithically epitaxial, high quality graphene on a SiC wafer (1), makes it a reliable alternative for some electronic applications, such as field effect transistors (FET), radio frequency (RF) power amplifiers, integrated circuits (IC), or sensors. In this work, we describe the fabrication and preliminary electrical characterizations of epitaxial graphene (EG) on a SiC substrate FET devices based on an alternative back gate architecture. We propose a new approach in which the FET device is built on a 4◦ off-axis cut, N+ doped 4H-SiC substrate (the back gate) with, on top of, it a 1μm semi-insulating homoepitaxial layer of SiC compensated with vanadium (the dielectric layer). EG will be used as FET conduction channel. Using this V-compensated dielectric layer is aimed to minimize effects on the FET characteristics such as from defects in the SiC crystal, especially below the FET active areas, which would have occurred when using ion implantation to create a buried gate. The EG film was grown by the high temperature Si sublimation method under an Ar ambient. Raman spectroscopy, Atomic Force Microscopy (AFM) and Scanning Electron Microscopy (SEM) were applied in the structural characterization of epigraphene. The lack of D-peak in Raman spectra, together with SEM and AFM images, indicate that high quality monolayer to few layer epitaxial graphene fully covering the SiC surface is deposited. The electrical characteristics of the EG channel-devices and the functionality of the bottom gate were examined with 2-probe and 4-probe method. The electrical properties of the FET devices were also investigated with 3 terminal configuration.

Novel Vitrified-Bond Ultra-Fine Grinding Technology for SiC Polishing

The present paper shows a new fixed abrasive bond-grit formulation aimed for best-in-class, low-cost and high-quality finished SiC wafer surfaces. Grinding wheels manufactured with this technology can accomplish ultra-smooth SiC (Ra = 0.55 nm and TTV < 1 μm) surfaces due to their unique bonding structure and their tailored grit size. Additionally, SiC wafers ground with these wheels exhibit reduced sub-surface crystal damage, mirror-like polished surface and improved wafer geometry while both the grinding forces and the wheel wear are kept low.

Advances in 200 mm 4H SiC Wafer Development and Production

200 mm diameter n-type 4H SiC wafers were produced from bulk crystals grown using a physical vapor transport (PVT) method. The configuration of the growth cell was modified to both allow for the growth of larger crystals with respect to the standard 150 mm process, and to induce a thermal environment necessary to increase the mass deposition rate. A 25% increase in deposition rate was achieved relative to the standard process. The resulting wafers exhibited resistivity uniformity comparable to commercial 150 mm product. Optical and x-ray techniques were used to evaluate wafer quality, and revealed surface and bulk crystal defect densities acceptable for epilayer growth.

Anisotropic Charge Transport Enabling High-Throughput and High-Aspect-Ratio Wet Etching of Silicon Carbide.

Wet etching of silicon carbide typically exhibits poor etching efficiency and low aspect ratio. In this study, an etching structure that exploits anisotropic charge carrier flow to enable high-throughput, external-bias-free wet etching of high-aspect-ratio SiC micro/nano-structures is demonstrated. Specifically, by applying a catalytic metal coating at the bottom surface of a SiC wafer while introducing patterned ultraviolet light illumination from its top surface, spatial charge separation across the wafer is achieved, i.e., photogenerated electrons are channeled to the bottom to participate in the reduction reaction of an oxidant in the etchant solution, while holes flow to the top to trigger oxidation of SiC and subsequent etching. Such design largely suppresses recombination-induced charge losses, and when used in combination with a top metal catalyst mask, the structure yields a remarkable vertical etching rate of 0.737µmmin-1 and an aspect ratio of 3.2, setting new records for wet-etching methods for SiC.

Analysis of the high-efficiency and low-damage abrasive processing mechanism for SiC based on the SPH simulation of single-grain indentation and scratching

During the wafer fabrication procedure, abrasive machining occupies a large proportion in time and economic cost, mainly including grinding, lapping, and polishing. The third-generation semiconductor materials, represented by SiC, have the properties of high hardness, large brittleness, and strong chemical inertness, which make abrasive machining more challenging. To improve the machining efficiency and quality, this paper applied the smoothed particle hydrodynamics (SPH) method to simulate the machining behavior of single abrasive grain for SiC wafer. The micro-mechanical mechanisms of the main influencing parameters, such as velocity, depth, and angle, were studied in abrasive machining for SiC wafer. First, it is proved that using SPH coupled with a finite element to study the mechanical effects of abrasive machining for SiC wafer is a feasible and useful method. Then, the explanations for the beneficial effects of ultrasonic vibration-assisted machining, high-speed machining, and other abrasive machining are provided through the analysis of the simulated results. In addition, the optimization basis for parameters such as scratching velocity, scratching depth, and ultrasonic vibration frequency is obtained. This research provides a good insight into implying the micro-mechanical mechanisms of abrasive machining and achieving the optimization for the abrasive machining of hard-brittle wafer materials, which help avoid the shortcomings of experimental research and produce economic benefits.

Chemically grafted polyurethane/graphene ternary slurry for advanced chemical–mechanical polishing of single-crystalline SiC wafers

Chemically grafted polyurethane/graphene ternary slurry for advanced chemical–mechanical polishing of single-crystalline SiC wafers

The effect of contact types on SiC polishing process

To better understand the effects of different contact types on polishing characteristics of SiC wafer, the different contact types during polishing are simplified as the self-rotation of diamond abrasives. Through molecular dynamics simulation, three different material removal modes are proposed and graphite structure after the wear of diamond was displayed. It is found that the material removal mode of 3C–SiC changes from cutting removal to adhesion removal via compression removal, and finally returns to cutting removal, with the increase of the abrasive linear velocity. The wear of diamond abrasive is the most serious when there is no self-rotation, and graphite will form after diamond is worn. When the abrasive only rolls forward, the wear of diamond abrasive is the least, and the material removal rate is also the least. The self-rotation of diamond abrasives can significantly reduce the structural damage of the workpiece and the increment of system temperature and potential energy. Also, the self-rotation of abrasives can reduce the tangential force, which leads to the decrease of friction coefficient. Based on the above results, it is proved that the self-rotation of abrasive particles in the polishing process cannot be ignored.

Machine learning methods for prediction analyses of 4H–SiC microfabrication via femtosecond laser processing

In this study, the effects of processing parameters on the geometry of femtosecond laser fabricated microgrooves on 4H–SiC wafer were investigated. To achieve a fast, accurate and intelligent manufacturing process, response surface methodology (RSM) and artificial neural network (ANN) method were applied for modeling and predicting the geometric features of microgrooves. In addition, analysis of variance (ANOVA) was employed to determine the most significant input variables on the responses. The RSM result showed that the third-order polynomial model equation was in high accordance with the experiments. During the analysis, laser power, scanning speed, and scanning times were set as input variables, and the depth, width and surface roughness (Ra) were set as response/output variables. Finally, the predictive capabilities of the RSM and ANN models were compared with each other in terms of coefficient of determine (R2), root mean squared error (RMSE), and relatively error (RE). The results indicated that the ANN method have a higher accuracy compared to those of the RSM model.

A general strategy for polishing SiC wafers to atomic smoothness with arbitrary facets

SiC is essential for epitaxial growth of graphene and promises to be an ideal material for next generation high-power electronics. The electronic properties of graphene are highly dependent on the facet on which it is grown. Therefore, the selection of facet provides an extra tuning parameter to obtain its desired characteristics. As one of the key factors of growing pristine graphene on SiC wafers, their roughness requires to be atomically smooth. In this work, we present a data-driven study of the grinding, mechanical polishing and chemical mechanical polishing (CMP) procedures applied to a SiC wafer with arbitrary facets. The phenomena and principles in the polishing steps are discussed. As specific facets of SiC have unique atomic arrangements, different recipes are required for the C and Si faces and their performances are investigated. The interesting, but rarely studied (1 1‾ 05) facet is taken as an example of a non-polar case to apply the procedures. It is found that the material removal rate (MRR) in mechanical polishing is directly related to the facet hardness. Hence, the MRR of the (1 1‾ 05) facet is the slowest in that process, however, during CMP its MRR is 18 times faster than the Si-face, hints the different chemical and physical polishing mechanism. Accordingly, polishing recipes are proposed that can be adjusted to create atomically smooth wafers of arbitrary facets of SiC.

A study of the magneto-controlled mechanical properties and polishing performance for single-crystal SiC used as a magnetorheological-elastomer polishing pad

Magnetorheological elastomers (MREs) are widely used in vibration control due to their excellent magneto-controlled mechanical properties. In this research, polyurethane-based MRE polishing pads were prepared and used for the polishing of single-crystal SiC to investigate the magneto-controlled mechanical properties, the magneto-polishing effect, and the mechanism of action thereof. The results show that the pre-structuring process is affected by parameters such as mass fraction and particle size of magnetic particles in MREs and curing magnetic field strength, different chain strings that demonstrate different magnetorheological effects are formed. The greater the mass fraction of magnetic particles and curing magnetic field strength, the more the MREs exhibit magnetorheological effects, especially so when the magnetic particles size of 3 μm. A series of 90 min polishing experiments on single-crystal SiC with original surface roughness (R a) 80 nm were conducted using an MRE pad. The results indicate that with the increase of polishing magnetic field strengths, the shear modulus of MRE polishing pads increases, the material removal rate (MRR) of the polishing process increases and R a decreases. As the magnetic field strength is increased from 0 mT to 335 mT, the shear modulus is increased from 1.392 MPa to 1.825 MPa (an increase of 31.1%), while MRR is increased from 706.3 nm h−1 to 835.3 nm h−1 (an increase of 18.3%), R a is decreased from 19.92 nm to 3.62 nm (an improvement in surface quality of 81.8%). The results show that the increase of the polishing magnetic field strengths changes the material modulus of the MRE polishing pads, which cause the decreases in the compressive and shear elastic deformation of the abrasive grains on the elastic substrate. This increases the positive pressure of the abrasive grains on the SiC wafer, which enhances the material-removal ability of the SiC wafer, thereby improving the surface quality of the wafer.

High-energy photoelectron spectroscopy of 6H-SiC wafer with Cr Kα excitation

A C-terminated SiC wafer was analyzed by high-energy photoelectron spectroscopy using monochromatic Cr Kα (5414.8 eV) radiation. The data include a survey scan and high-resolution spectra of Si 1s, Si 2s, Si 2p, C 1s, and O 1s core levels.

Создание темплейтов для гомоэпитаксиального роста 3C-SiC методом прямого сращивания пластин карбида кремния различающихся политипов

An approach of direct bonding of SiC wafers of differing polytypes has been implemented in order to create a template for cubic 3C-SiC homoepitaxy. Heteroepitaxial 3C-SiC layers grown by chemical vapor deposition were transferred onto a hexagonal 6H-SiC wafer. The results of structural characterization showed that the quality of 3C-SiC sublimation epitaxy on the templates is comparable to the level of epitaxy of cubic silicon carbide by chemical vapor deposition method. It was confirmed that the 3С-SiC layer transferred onto the 6H-SiC substrate plays the role of a crystalline "seed" that determines cubic polytype of the overgrown SiC layer.

Templates for homoepitaxial growth of 3C-SiC obtained by direct bonding of silicon carbide wafers of differing polytype

An approach of direct bonding of SiC wafers of differing polytypes has been implemented in order to create a template for cubic 3C-SiC homoepitaxy. Heteroepitaxial 3C-SiC layers grown by chemical vapor deposition were transferred onto a hexagonal 6H-SiC wafer. The results of structural characterization showed that the quality of 3C-SiC sublimation epitaxy on the templates is comparable to the level of epitaxy of cubic silicon carbide by chemical vapor deposition method. It was confirmed that the 3C-SiC layer transferred onto the 6H-SiC substrate plays the role of a crystalline "seed" that determines cubic polytype of the overgrown SiC layer. Keywords: Silicon carbide, polytypes, direct bonding, templates, sublimation epitaxy.

Non-contact grinding/thinning of silicon carbide wafer by pure EDM using a rotary cup wheel electrode

The significantly increased stability of third-generation semiconductors, both mechanically and chemically, presents a significant challenge to traditional wafer grinding. This study develops pure electrical discharge machining as an alternative for non-contact wafer grinding and thinning to achieve high precision and low cost. This method employs a copper-made rotary cup wheel as the tool electrode to replace the conventional diamond wheel to realize electrical discharge grinding. A prototype is built to evaluate the new process with single-crystal SiC. Aiming at ultra-precision machining, the material response of SiC to both single and consecutive discharge is elucidated. The influencing mechanism of pulse conditions on hard, brittle crystalline SiC material is demonstrated via experiments and simulation. Further, the material removal behavior, grinding stability, surface integrity, wafer shape accuracy, and process-induced subsurface damage are comprehensively investigated via single and consecutive discharge experiments under various conditions. In addition, the extreme precision that is achievable by contemporary EDM technology is explored. As a result, a 30 μm thin Φ20 mm SiC wafer with a subsurface damaged layer <1 μm was obtained, showing the potential of EDM for the processing of third-generation semiconductor wafers.

Efficient and slurryless ultrasonic vibration assisted electrochemical mechanical polishing for 4H–SiC wafers

This paper proposes a slurryless, highly efficient polishing method called ultrasonic vibration assisted electrochemical mechanical polishing (UAECMP) to realize 4H–SiC wafers with subnanometer surface roughness. UAECMP involves using ultrasonic vibration to simultaneously assist anodic oxidation of the SiC surface and mechanical removal of the generated oxide layer. The performance of UAECMP was evaluated by experiments and theoretical analyses. For a 4H–SiC (0001) surface, UAECMP achieved a material removal rate (MRR) of 14.54 μm/h, which was 4.5 times greater than that of ordinary electrochemical mechanical polishing (ECMP) and 290 times greater than that of mechanical polishing. Ultrasonic vibration increased the anodic oxidation rate by introducing local transient strain to the SiC surface and increasing the temperatures of the polishing area and electrolyte. The effect increased with the amplitude of the ultrasonic vibration. However, increasing the ultrasonic vibration amplitude also increased the surface roughness due to the large fluctuations of polishing marks caused by the grinding stone and SiC surface impact and the increasing residual oxide. Therefore, we propose a high-efficiency and -quality polishing process for SiC wafers that combines UAECMP and ECMP. The proposed polishing process may help simplify the existing manufacturing process for SiC wafers.