Si p-MOSFETs Research Articles

Study of Strained-SiGe Channel P-MOSFET Using Silvaco TCAD: Impact of Channel Thickness

Compressively strained SiGe is an interesting channel material for sub 45 nm p-MOSFETs because of its superior hole mobility (up to 10x over bulk Si channels) and compatibility with current Si manufacturing technologies. In this work, the impact of heterostructure composition and SiGe channel thickness on the electrical characteristics of p-MOSFET are studied. Using strained Si0.8Ge0.2 p-MOSFET, the thickness was altered to a few thicknesses of 3 nm, 5 nm, 7 nm, and 9 nm respectively. The optimal thickness was then used for Ge compositions (x = 0.2). The project was realized utilizing computer-aided Silvaco TCAD tools, with ATHENA tools creating the p-MOSFET structure and ATLAS tools doing the device simulation. The strained-Si1-xGex p-MOSFET and the Si p-MOSFET were compared in terms of their performances. The ID-VG and ID-VD characteristics, as well as the threshold voltage, VTH extraction, were the focus of the device simulation. The 7 nm thickness strained-Si0.8Ge0.2 p-MOSFET exhibited lower VTH than other SiGe thicknesses and the Si p-MOSFET which is VTH = 0.074 V. The lower threshold voltage of the strained-Si0.8Ge0.2 with 7 nm thickness indicating that the strained-Si1-xGex contributed to the decreased power consumption. In addition, the extracted IDsat for the strained-Si0.8Ge0.2 p-MOSFET with 7nm thickness provided higher IDsat compared to conventional Si p-MOSFET and other SiGe thicknesses devices. As compared to Si p-MOSFETs, the output characteristics of the strained-Si1-xGex demonstrated a drain current improvement by a factor of 1.01.

Dependences of the hole mobility in the strained Si pMOSFET and gated Hall bars formed on SiGe/Si(1 1 0) on the channel direction and the strained Si thickness

Strained Si/relaxed SiGe/Si(110) heterostructures are gaining interest as an attractive candidate for a Si-wafer-based material for semiconductor devices with enhanced performances and lower power consumption, since a significant enhancement of the hole mobility has been demonstrated in this system. In this paper, dependences of the hole mobility on the channel direction and the strained Si layer thickness are discussed to reveal detailed transport properties of the (110)-oriented pMOSFETs. A significant anisotropy was found regarding the hole mobility, and the 1¯10 direction was found to be a preferable channel direction regarding the hole mobility. Also, it was found that strained Si layer should be sufficiently thin to achieve a high mobility. The physical mechanisms of the anisotropy and the thickness dependence of the hole mobility are discussed by considering the configuration of defects and the valence band structure.

(Invited) Engineering Strain, Defects, and Electronic Properties of (110)-Oriented Strained Si

Strain engineering of group IV semiconductors has been extensively investigated with an aim to produce high mobility platform for high performance electronic devices. In particular, combination of strain and 3D structures requires elaborate engineering of strain to obtain optimum effect. Effects of utilization of non-(001)-oriented channel and anisotropic strain are major factors to be considered. The lattice structure of a strained material is generally anisotropic. Symmetry of the lattice structure is expected to have significant influence on electrical properties of crystals, which should be taken into consideration for advanced application of the lattice deformation. In addition, anisotropy in the lattice structure significantly affects the generation of defects during heterostructure formations, which can result in even larger asymmetry in the lattice structure. As a matter of fact, it is found that strain components and morphology of defects are highly asymmetric in the strained Si/SiGe heterostructures formed on (110) substrates. Recently, significant enhancement of the hole mobility was demonstrated in the topmost strained Si film. In this presentation, formation mechanism of the highly asymmetric strain in this heterostructure system and its influence on the properties of strained Si pMOSFET are discussed.Through a computational study of strain effect on the valence band structure, we found that the lowering of the hole effective mass due to strain is expected to be larger on (110) surface than on (001) surface. According to the calculation, the cyclotron effective mass of a hole on (110)-oriented strained Si can be lowered to ~ 0.2 m0 by strain. On the other hand, it was found that the minimum hole effective mass is ~ 0.3 m0 in the case of the (001)-oriented strained Si film. In addition, the result of the calculation shows that the hole effective mass on the (001)-oriented strained Si does not decrease with the increase of strain. These results motivated us to carry out experimental investigation on the growth and electrical properties of (110)-oriented strained Si. Strain-relaxed SiGe was employed as a buffer layer for strained Si layer. The growths were carried out using solid-source molecular beam epitaxy. On a Si(110) substrate, SiGe layer is subjected to biaxial compressive stress which induces glides of partial dislocations on (111) and (11-1) planes. Since the Burgers vectors of these partial dislocations are perpendicular to the in-plane axis [-110], the resultant strain relaxation is highly anisotropic. Accordingly, the surface morphology is also highly anisotropic. It was confirmed that strain in the topmost Si layer is also highly anisotropic in accordance with the lattice parameters of the SiGe layer. These anisotropic features play significant roles in electronic properties of the strained-Si MOSFET formed on this structure in the following manners. First, both the surface and the crystalline morphologies are almost homogeneous in the [-110] direction, for which the relaxation time is expected to be long for the motion in the [-110] direction. Secondly, the anisotropic strain shifts the valence band edges of the layers so that the holes are effectively confined to the high-mobility strained Si layer. A pMOSFET was fabricated on a (110)-oriented strained Si/SiGe structure and hole effective mobility was evaluated by IV and CV measurements. A significantly high hole effective mobility (480 cm2/Vs) was obtained in a pMOSFET with the [-110] channel. High hole mobility in the (110)-oriented strained Si with [-110] channel was also confirmed by gated Hall measurements.

BSIM3 model parameter extraction and performance analysis of a strained p-MOSFET for digital applications

Strain is one of the conventional methods used to enhance the mobility of carriers in metal–oxide–semiconductor field-effect transistors (MOSFETs). The strain is generated due to the lattice mismatch between the thin Si layer and underlying SiGe layers and reduces the effective mass of holes and inter-subband scattering. A compact model for such devices is essential to promote the design of very large-scale integration (VLSI) circuits using strained p-MOSFETs. In this paper, for the first time we propose to use the BSIM3 model for biaxially strained p-MOSFETs, using a proper parameter extraction method. The extracted model parameters are validated by comparing the results with technology computer-aided design (TCAD) simulations and a simple analytical model. The average error in the direct-current (DC) and alternating-current (AC) characteristics of the model is estimated to be below 1.5%. Finally, the extracted model is used to analyze the performance of several digital gates, including inverter, NAND, NOR, and static random-access memory (SRAM) cells, based on the strained p-MOSFET as a key circuit component. The simulation results show significant performance improvements of the gates in terms of the area, propagation delay, dynamic power consumption, static noise margin, and functional symmetry. By using strained p-MOSFETs in the SRAM cell, the active area of transistors can be reduced by up to 28.8% while at the same the time static power consumption is reduced by 4.8%, the static noise margin is increased by 10.5%, and the write access time is reduced by about 15.6%. These results not only suggest that the strained Si p-MOSFET can improve the performance of VLSI circuits but also confirm that the BSIM3 model with an appropriate parameter extraction method can be used for the design of digital circuits using strained p-MOSFETs.

Strain relaxation process and evolution of crystalline morphologies during the growths of SiGe on Si(110) by solid-source molecular beam epitaxy

In a previous study, we reported on a (110)-oriented strained Si pMOSFET with an effective hole mobility as high as 480 cm2/Vs. To impose the lattice strain on the Si channel layer, strain-relaxed SiGe buffer layer is utilized. Defect formation is requisite for strain relaxation in SiGe layer, and at the same time, has the adverse effects for electrical properties of the strained Si film. Therefore, it is necessary to control the formation of the crystalline defects. The aim of this study is to investigate the evolution of the crystalline morphology during the growth of SiGe layers by solid source molecular beam epitaxy, which is utilized to optimize the structural parameters of the strain-relaxed SiGe buffer layers. It is revealed in this study that the lattice strain in SiGe formed on Si(110) begin to relax at a lower film thickness than in the case of SiGe on Si(001). Orientation dependences of surface morphology and degree of strain relaxation are found to be dependent on Ge composition. The development process of the growth twin is also discussed. It is shown that the growth twin generation is effectively suppressed by the composition grading technique.

Impact of Source to Drain Tunneling on the Ballistic Performance of Si, Ge, GaSb, and GeSn Nanowire p-MOSFETs

We investigated the effect of material choice and orientation in limiting source to drain tunneling (SDT) in nanowire (NW) p-MOSFETs. Si, Ge, GaSb, and Ge 0.96 Sn 0.04 nanowire MOSFETs (NWFETs) were simulated at a scaled gate length (L G ) of 10 nm, using rigorous ballistic quantum transport simulations. To properly account for the non-parabolicity and anisotropy of the valence band, the k·p method was used. For each material, we simulated a set of six different transport/confinement directions, at a fixed OFF-state current (I OFF ) of 100 nA/μm and supply voltage V DD = -0.5 V to identify the direction with the highest ON-current (I ON ). For Ge, GaSb, and GeSn [001]/110/110 oriented NWFETs, with [001] being the direction of transport and 110, 110 being the directions of confinement for the nanowire, showed the best ON-state performance, compared to other orientations. Our simulation results show that, despite having a higher percentage of SDT in OFF-state than silicon, GaSb [001]/110/110 NWFET can outperform Si NWFETs. We further examined the role of doping in limiting SDT and demonstrated that the ON-state performance of Ge and GeSn NWFETs could be improved by reducing the doping in the source/drain (S/D) extension regions. Our simulation result show that with properly chosen channel transport orientation and S/D doping concentration, performance of materials with high hole mobility can be optimized to reduce the impact of SDT and provide a performance improvement over Si-channel based p-MOSFETs.

Improved digital performance of hybrid CMOS inverter with Si p-MOSFET and InGaAs n-MOSFET in the nanometer regime

Using extensive numerical analysis we study the digital performance of 30-nm hybrid CMOS inverters comprising Si p-MOSFETs and In0.70Ga0.30As n-MOSFETs in terms of rise time (tr), fall time (tf), propagation delay (td), noise margins high (NMH) and low (NML) of an inverter, and also the oscillation frequency (fosc) of a ring oscillator with and without considering NBTI effects. Our findings show that for a hybrid CMOS inverter, tf and td exhibit 83% and 73% reduction, respectively, while NMH and NML show improvement of 24.4% and 42.2%, respectively, in relation to those found in the Si CMOS inverter at the ratio of widths of p-MOSFET and n-MOSFET equal to 3. fosc of a 3-stage hybrid ring oscillator exhibits 272.5% improvement over its Si counterpart. Our proposed hybrid inverters outperform equivalent Si inverters for digital applications with and without NBTI degradation at more advanced technology node while dissipating marginally higher OFF-state power.

InGaSb-on-insulator p-channel metal-oxide-semiconductor field-effect transistors on Si fabricated by direct wafer bonding

InGaSb-on-insulator (InGaSb-OI) and InAs/InGaAs/InAs-on-insulator (InAs/InGaAs-OI) structures have been realized on Si by a direct wafer bonding (DWB) technology using atomic-layer-deposition Al2O3. While strain introduced in InGaSb channel layers grown on InAs can enhance the hole mobility of the Sb-based channel layers, a difficult issue of fabricating InGaSb-OI wafers is to obtain a smooth InGaSb surface, which is mandatory for wafer bonding. In this study, the surface of a 20-nm-thick In0.185Ga0.815Sb channel grown on an InAs (100) substrate and an InAs (2.5 nm)/In0.185Ga0.815Sb (20 nm)/InAs (2.5 nm) channel with a 20-nm-thick GaSb buffer layer grown on an InAs (100) substrate by metal-organic chemical vapor deposition have a root mean square of the surface roughness as low as 0.16 and 0.22 nm, respectively, over a scan area of 10 × 10 μm2, which are smooth enough to employ the wafer bonding. As a result, the fabrication of the InGaSb-OI wafers by the DWB and the operation of InGaSb-OI p-channel metal-oxide-semiconductor field-effect transistors (p-MOSFETs) by using the DWB wafers are demonstrated. Also, the performance of InGaSb-OI p-MOSFETs is found to be improved by inserting ultrathin InAs layers between InGaSb and insulating buried oxide layers. An InGaSb-OI and an InAs/InGaAs-OI p-MOSFET under the accumulation-mode operation exhibit a peak mobility of ∼161 and ∼273 cm2/V s, respectively. The channel hole mobility of the InGaSb-OI p-MOSFET is higher than that of the GaSb-on-insulator (GaSb-OI) p-MOSFET and can exceed that of Si p-MOSFETs.

Impact of sidewall spacer on n-InGaAs devices and hybrid InGaAs/Si CMOS amplifiers in deca-nanometer regime

In this paper, we report, for the first time, the influence of the sidewall spacers (SWS) on the analog performance of InGaAs nMOSFETs at channel lengths of 32 and 22 nm. The study is further extended to the circuit level in which the impact of spacer layer on hybrid CMOSFETs comprising InGaAs nMOSFETs and Si pMOSFETs is thoroughly investigated in analog domain. Using extensive numerical analysis we study the impact of SWS layers on various device parameters e.g., transconductance (gm), transconductance efficiency (gm/ID), output conductance (gd) and intrinsic gain (gm/gd) related to analog applications. Then, the hybrid CMOS current source load amplifier is studied in terms of voltage gain, total capacitance (CTotal) and gain bandwidth product (GBW). The simulation scheme is validated with reported experimental data in the literature. Our findings reveal that all the parameters at the device level, except gd exhibit improved performance for higher value of spacer k. On the contrary, gd decreases with reduced k-value and becomes weakly sensitive to the variation in spacer length (Lsp), for the InGaAs nMOS device having channel lengths (Lg) of 22 and 32 nm. At the circuit level, for the hybrid CMOS amplifier, we found that the dc-gain and CTotal exhibit larger value for higher value of Lsp, while GBW shows higher value for reduced Lsp. Our investigation suggests that improved analog performance of InGaAs nMOSFETs with suitable SWS engineering may be achieved at more advanced technology nodes.

Reduction of Dislocation Densities of Ge Layers Grown on Si Substrates by Using Microwave Plasma Heating and Fabrication of High Hole Mobility MOSFETs on Ge Layers

We have developed a microwave plasma heating technique to rapidly heat the transition metal. W/SiO2 layers were deposited on Ge/Si heterostructures. By heating the W, dislocations in Ge layers originated from lattice mismatch between Ge and Si crystals were reduced drastically. We have fabricated p- MOSFETs on Ge/Si substrates and realized higher mobility of about 380 cm2/ Vs than that of Si p-MOSFET.

High Performance Tri-Gate Germanium-on-insulator Based Junctionless Nanowire Transistors

With feature size of transistors reducing down to sub-20 nm nodes, high mobility channel materials and novel device structures are critical to further improve the performance of transistors. Junctionless nanowire transistor (JNT) is recently proposed and regarded as promising candidate structure due to its simple fabrication process and excellent electronic properties [1]. Germanium-on-insulator (GOI) substrate is regarded as promising substrate due to its advantages of both Ge and on-insulator substrates. Although GOI-based JNTs have been reported [2,3], the performances are far from satisfactory. In this work, we fabricated high performance GOI-based JNTs with much smaller dimensions, where channel length and width are both less than 100 nm, and demonstrated their fabrication process and electrical properties in detail. Fig.1 shows SEM images of tri-gate JNTs with different dimension, (a)W/L=40nm/70nm and (b) W/L=40nm/100nm, respectively. Fig.2 shows TEM image of a GOI sample with Tge=10 nm. The original thickness of Ge film was about 50 nm. We reduced Tge down to 10 nm using a simple wet retching method as reported in our previous work [4]. Fig.3 shows the schematic diagrams of fabrication process. To reduce costs and improve efficiency, we used both optical lithography (OL) and electron beam lithography (EBL). First, we used OL to define active region of the devices. GeO2 channel passivation was carried out by ozone oxidation at 300 °C for 30 min. Then EBL was carried out to define the channel and gate electrode, which had much smaller dimensions. Finally, we used OL and lift-off process to define measuring electrodes. Fig.4 (a) shows Id-Vg characteristics of JNTs with Tge =20nm and Tge=10nm, respectively. It can be observed that Ion/Ioff ratio of the JNT with Tge=10nm is larger than 105 at Vd= -1V. The subthreshold slope at Vd= -0.1V and the drain induced-barrier lowering (DIBL) are estimated to be 110 mV/dec and 140 mV/V, respectively. With decrease of Tge, we get better device performance. Fig.4 (b) shows the Id-Vd characteristics of JNT with W/L=40nm/70nm, Na=1018 cm-3 and Tge=10nm. Liner and saturation regions are clearly exhibited. Fig.5 (a) shows the influence of temperature on Id-Vg characteristics of JNTs with W/L=40nm/70nm, Na=1018cm-3 and Tge =10nm. It can be observed that with increase of temperature leakage current increased dramatically. Fig.5 (b) shows mobility of the same JNT. The reported mobility values of a GOI JNT with Na= 1019 cm−3 [2] and a conventional Si pMOSFET [5] are also plotted for comparison. The peak mobility is larger than 200 cm2V-1S-1, which is close to that of bulk germanium with a doping concentration of 1018 cm−3. In summary, we fabricated high performance GOI-based JNTs using a Si-compatible process which combines OL and EBL. Good Ion/Ioff ratio, subthreshold slope, DIBL and mobility are extracted, which indicating that ultra-thin body GOI-based JNTs are promising for high performance circuits. The device performance can be improved by optimizing the fabrication process and device structure. Acknowledgments: This work was supported in part by the National Natural Science Foundation of China (No. 61306105). [1] J. P. Colinge et.al, Nat. Nanotechnol. 5, 225, 2010. [2] D. D. Zhao et al. Jpn. J. Appl. Phys., Part 1, 51, 04DA03, 2012. [3] R. Yu et al., Phys. Status Solidi RRL 8, 65, 2014. [4] C. Sun et al. ECS Solid State Lett. 4, P43, 2015. [5] S. Takagi et al, IEEE Trans. Electron Devices, 41,2363, 1994. Figure 1

Activation Energies for Oxide- and Interface-Trap Charge Generation Due to Negative-Bias Temperature Stress of Si-Capped SiGe-pMOSFETs

We investigate negative-bias temperature instabilities in SiGe pMOSFETs with SiO 2/HfO 2 gate dielectrics. The measured activation energies for interface-trap charge buildup during negative-bias temperature stress are lower for SiGe channel pMOSFETs with SiO 2/HfO 2 gate dielectrics and Si capping layers than for conventional Si channel pMOSFETs with SiO 2 gate dielectrics. Electron energy loss spectroscopy and scanning transmission electron microscopy images demonstrate that Ge atoms can diffuse from the SiGe layer into the Si capping layer, which is adjacent to the SiO 2/HfO 2 gate dielectric. Density functional calculations show that these Ge atoms reduce the strength of nearby Si–H bonds and that Ge–H bond energies are still lower, thereby reducing the activation energy for interface-trap generation for the SiGe devices. Activation energies for oxide-trap charge buildup during negative-bias temperature stress are similarly small for SiGe pMOSFETs with SiO 2/HfO 2 gate dielectrics and Si pMOSFETs with SiO 2 gate dielectrics, suggesting that, in both cases, the oxide-trap charge buildup likely is rate-limited by hole tunneling into the near-interfacial SiO 2.

Impacts of virtual substrate doping on high frequency characteristics of biaxially strained Si PMOSFET

Formation of a parasitic channel in biaxially strained Si channel p-MOSFET, degrades performance of the device. In this paper the effect of SiGe (virtual substrate) doping on formation of parasitic channel and high frequency characteristics of the strained MOSFET has been studied. Simulation results, indicate that increasing virtual substrate’s doping from e.g. 4×1015cm−3 to 4×1017cm−3 effectively eliminates parasitic channel by reducing hole concentration from 1×1017cm−3 to 1×1011cm−3 in the parasitic channel. This improves MOSFET’s characteristics including parasitic capacitances and channel length modulation. Also it has been demonstrated that the highest unity-gain bandwidth might be achieved at doping level of 4×1017cm−3.

Performance of CMOS With Si pMOS and Asymmetric InP/InGaAs nMOS for Analog Circuit Applications

We propose a novel hybrid CMOS comprising a Si-channel pMOSFET and an asymmetric InP/InGaAs nMOSFET in the nanometer regime for analog applications. The performance of such a CMOS is evaluated in terms of voltage gain and gain-bandwidth (GBW) product at two different channel lengths (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> ), 50 and 30 nm, using extensive device simulations. Our investigations reveal that the maximum gain of the hybrid CMOS inverter is improved by 37.5% and 92.1% for asymmetric In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.75</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.25</sub> As nMOS devices with InP drain at L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> = 30 nm for W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p</sub> /W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sub> = 3 and 8, respectively, as compared with an equally sized Si inverter having W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p</sub> /W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sub> = 3. In addition, GBW product of hybrid CMOS (HAS3) comprising asymmetric In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.75</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.25</sub> As nMOSFET with InP source and Si pMOSFET is increased by 148.1% and 260.4% at L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> = 30 and 50 nm, respectively, for W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p</sub> /W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sub> = 3, compared with its Si counterpart. Furthermore, the HAS3 device yields the highest GBW peak, unity current gain frequency, and maximum oscillation frequency as compared with other hybrid and Si CMOS devices at L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> = 30 and 50 nm.

Experimental Study on NBTI Degradation Behaviors in Si pMOSFETs Under Compressive and Tensile Strains

In this letter, we experimentally investigated the effects of four types of strains, uniaxial tensile strain, uniaxial compressive strain, biaxial tensile strain, and biaxial compressive strain, on the negative bias temperature instability (NBTI) degradation behaviors of Si pMOSFETs. The strains were applied using a wafer bending system to avoid processing effects on the NBTI characteristics as a result of strain engineering. We confirm experimentally, for the first time, that both uniaxial and biaxial compressive strains are advantageous in terms of the NBTI improvement in Si pMOSFETs. However, the NBTI reliability was degraded under both uniaxial and biaxial tensile strains. These results could not be explained by considering only the gate leakage current change due to the strain. The strain-induced modulation of the interaction between the carriers and Si-H bonds at the interface must also be considered.

Improved Degradation and Recovery Characteristics of SiGe p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors under Negative-Bias Temperature Stress

This paper describes the degradation and recovery characteristics of SiGe pMOSFETs with a high-k/metal gate stack under negative-bias temperature instability (NBTI) stress. The threshold voltage instability (ΔVth) of SiGe pMOSFETs shows an increased percentage of recovery (R) as well as lower degradation than those of control Si pMOSFETs. It is found that the recovery characteristics of SiGe and Si pMOSFETs have similar dependencies on various stress conditions, and the increased R of SiGe pMOSFETs is mainly attributed to their lower degradation characteristic. Under real operating conditions, most of the ΔVth caused by hole trapping would be rapidly recovered through a fast recovery process, and newly-generated interface traps during the stress would determine the degradation level of Vth. The SiGe pMOSFETs show lower stress-induced interface traps; thus, they would display more reliable NBTI characteristics than Si pMOSFETs under real operating conditions.

Towards understanding hole traps and NBTI of Ge/GeO2/Al2O3 structure

Graphical abstractDisplay Omitted HighlightsHole trapping and NBTI is substantial and the threshold voltage shift can be close to 1V for Ge/GeO2/Al2O3.A new energy switching model has been proposed for the charging and discharging of hole traps for Ge/GeO2/Al2O3.Unlike Si sample, the energy level of hole traps rises after charging and lowers after neutralization for Ge sample. The high hole mobility of Ge makes it a strong candidate for replacing Si in future generation of CMOS technology. The Ge/GeO2/Al2O3 offers one of the lowest interface states, but there is little information available on its reliability. For Si pMOSFETs, NBTI limits their lifetime and hole traps in gate dielectric play a major role in NBTI. The objective of this work is to investigate the hole traps of Ge/GeO2/Al2O3 structure. Wherever possible, the Si/SiON or Si/SiON/High-k will be used as a benchmark. It is found that hole trapping and NBTI is substantial and the threshold voltage shift can be close to 1V for Ge/GeO2/Al2O3. A new model has been proposed to explain the charging and discharging behavior of hole traps. Unlike Si sample, the energy level of hole traps rises after charging and lowers after neutralization for Ge sample.

(Invited) Reliability of SiGe Channel MOS

We report extensive experimental results on the Negative Bias Temperature Instability (NBTI) of SiGe channel pMOSFETs as a function of the main gate stack parameters. These results clearly show that this high-mobility channel technology offers a significantly improved NBTI robustness compared to Si-channel devices, which can virtually eliminate this critical reliability issue for sub-1 nm EOT devices. The intrinsically superior NBTI robustness is understood in terms of a favorable energy decoupling between the SiGe channel and the gate dielectric defects. Thanks to this effect, both a significantly reduced time-dependent variability in nanoscaled SiGe devices and a reduced low-frequency noise are also observed. Other reliability mechanisms, such as Channel Hot Carriers and Time-Dependent Dielectric Breakdown are shown not to be showstoppers. All these aspects underscore the SiGe channel technology as a very promising alternative to Si pMOSFETs for future CMOS technology nodes.

Study on gate capacitance-voltage characteristics of strained-SiGe pMOSFET

The gate capacitance-voltage (C-V) characteristic of strained SiGe pMOSFET is very different from that of bulk Si pMOSFET, and can be strongly affected by the channel doping. In this paper, we first study the formation mechanism of the "plateau" which can be observed in the gate C-V characteristics of strained SiGe pMOSFET, and then present a physics based analytical model to predict the gate C-V characteristic of strained SiGe pMOSFET. It is found that this plateau is channel doping dependent. The results from the model are compared with the experimental results and they are found to be in excellent agreement with each other, giving the evidence for its validity.

Buried Silicon-Germanium pMOSFETs: Experimental Analysis in VLSI Logic Circuits Under Aggressive Voltage Scaling

In this paper, the potential of Silicon-Germanium (SiGe) technology for VLSI logic applications is investigated from a circuit perspective for the first time. The study is based on experimental measurements on 45-nm SiGe pMOSFETs with a high- κ/metal gate stack, as well as on 45-nm Si pMOSFETs with identical gate stack for comparison. In the reference SiGe technology, an innovative technological solution is adopted that limits the SiGe material only to the channel region. The resulting SiGe device merges the higher speed of the Ge technology with the lower leakage of the Si technology. Appropriate circuit- and system-level metrics are introduced to identify the advantages offered by SiGe technology in VLSI circuits. Analysis is performed in the context of next-generation VLSI circuits that fully exploit circuit- and system-level techniques to improve the energy efficiency through aggressive voltage scaling, other than low-leakage techniques. Analysis shows that the SiGe technology has more efficient leakage-delay and dynamic energy-delay trade-offs at nominal supply, compared to Si technology. Moreover, it is shown that the traditional analysis performed at nominal supply actually underestimates the benefits of SiGe pMOSFETs, since the speed advantage of SiGe VLSI circuits is further emphasized at low voltages. This demonstrates that SiGe VLSI circuits benefit from aggressive voltage scaling significantly more than Si circuits, thereby making SiGe devices a very promising alternative to Si transistors in next-generation VLSI systems.