Improved digital performance of hybrid CMOS inverter with Si p-MOSFET and InGaAs n-MOSFET in the nanometer regime

Abstract

Using extensive numerical analysis we study the digital performance of 30-nm hybrid CMOS inverters comprising Si p-MOSFETs and In0.70Ga0.30As n-MOSFETs in terms of rise time (tr), fall time (tf), propagation delay (td), noise margins high (NMH) and low (NML) of an inverter, and also the oscillation frequency (fosc) of a ring oscillator with and without considering NBTI effects. Our findings show that for a hybrid CMOS inverter, tf and td exhibit 83% and 73% reduction, respectively, while NMH and NML show improvement of 24.4% and 42.2%, respectively, in relation to those found in the Si CMOS inverter at the ratio of widths of p-MOSFET and n-MOSFET equal to 3. fosc of a 3-stage hybrid ring oscillator exhibits 272.5% improvement over its Si counterpart. Our proposed hybrid inverters outperform equivalent Si inverters for digital applications with and without NBTI degradation at more advanced technology node while dissipating marginally higher OFF-state power.