Si p-MOSFETs Research Articles

Hot-carrier stress effects on the amplitude of Random Telegraph Signals in small area Si p-MOSFETS

This paper studies the effect of avalanche hot-carrier (HC) stress on the amplitude of pre-existing Random Telegraph Signals (RTSs) in small area Si p-MOSFETs. It is shown that the RTS amplitude of a particular oxide trap increases after HC stress, both in linear operation and in saturation. From this, it is concluded that the effect of such a trap on the carrier transport in a small area MOSFET is also determined by the charges present at the interface and in the oxide. The impact of the observations on the RTS based modeling of 1 f flicker noise in MOSFETs will be briefly addressed.

Design of Si and SiGe p-channel SOI MOSFET

There is a great deal of interest in combining SOI and SiGe technologies. In this work we present a systematic study of scaling properties of n + and p + gate SOI Si and SiGe p-MOSFETs by using two-dimensional numerical simulation. It was found that for both Si and SiGe devices, n + gate is better suited for the design of fully depleted devices while for the design of partially depleted or near-fully depleted devices p + gate is a better choice. Overall, the n + gate is a better solution since we can design a device that is very low doped, fully depleted, satisfies all the design criteria, has small threshold voltage ( V TH) sensitivity to the silicon film thickness ( t Si) and sharp subthreshold slope. The SiGe device shows increase in linear transconductance of 24%, smaller increase in saturation transconductance, improved current drive and extended range of design options. Our results also indicate that reduction of the t Si is more effective in controlling the DIBL and SCE in low doped n + gate designs, than increase in doping. The n + gate design requires p + doping spike for threshold voltage adjustment. For the case of Si p + gate design, V TH can be easily adjusted by changing the doping level in the channel. Since the doping level used is relatively high this naturally leads to partially depleted devices in order to avoid large dependence of V TH on the t Si. However, a fully depleted device can be designed to have low dependence of V TH on the t Si. This is done by utilizing the t Si dependence of: (1) the total charge under the gate; and (2) source-body potential barrier. If the thickness is reduced, the first effect reduces while the second one increases the threshold voltage making the dependence of V TH on the thickness acceptable. The p + gate SiGe SOI p-MOSFET requires high body doping levels and exhibits large subthreshold slope and reduced transconductance.

Operation of SiGe channel heterojunction p-MOSFET

We report a Monte Carlo analysis of SiGe p-MOSFET in comparison with conventionally designed Si p-MOSFET. The purpose of our study is to quantify the contribution in device performance enhancement of the separation of holes from rough Si/SiO 2 interface and of the SiGe transport properties. In SiGe p-MOSFET, the effective channel mobility is increased by a factor 2.6 with 60% of this improvement due to the confining of holes in a potential well. The device performances I D, g m , and f T are improved by at least 55% only due to the strain-induced lowering of the hole effective mass in SiGe.

Theory and observation of enhanced, high field hole transport in Si/sub 1-x/Ge/sub x/ quantum well p-MOSFETs

We report on the observation of enhanced high field hole velocity in strained Si/Si/sub 1-x/Ge/sub x//Si quantum wells. This effect manifests itself in the drive current capability of nanometer scale p-channel Quantum Well Metal-Oxide-Semiconductor-Field-Effect-Transistors (p-QWMOSFETs). The high-field transport of a two-dimensional hole gas confined in a Si/Si/sub 1-x/Ge/sub x//Si quantum well is formulated and solved. The results indicate an increase in the hole saturated drift velocity in strained SiGe quantum wells with increasing Ge mole fractions up to x=0.5. This is a consequence of the optical phonon spectrum of the strained SiGe alloy remaining Si-like (i.e., high energy) while the carrier transverse effective mass decreases with higher Ge content. To investigate the theoretical prediction of increased high-field drift velocity, p-QWMOSFETs were fabricated with Si/Si/sub i-x/Ge/sub x//Si quantum well heterostructures grown by Molecular Beam Epitaxy (MBE) with varying Ge mole fractions, x. The fabrication sequence maintained a low thermal budget to prevent strain relaxation in the SiGe layer and involved a mixed optical/electron beam lithography scheme to define junction-isolated transistors with a minimum drawn gate lengths of 200 nm. The measured saturated transconductance, g/sub msat/, of the p-QWMOSFETs were 20-50% higher than that of a reference Si pMOSFET under equivalent biasing conditions. The importance of this g/sub msat/ increase for high-speed, low-power VLSI applications is discussed.

A multi-band model for the hole transport in silicon at high energies

A new microscopic silicon model for hole transport at high electric fields featuring two valence bands in a finite Brillouin zone is presented. The band parameters and the electron-phonon coupling constants were determined by best fitting the density of states and the experimental and theoretical results for transport properties in the low and intermediate field-strength range. Hole impact ionization has been introduced following a new scheme that goes beyond the limitations contained in the Keldysh formula. The present model, coupled to an analogous model already developed for electrons, allows study of bipolar transport silicon devices. Applications to bulk Si and Si p-MOSFETs are presented.