Si Metal-oxide-semiconductor Field-effect Transistors Research Articles

Comparison of Si and SiC MOSFETs responses to electrical stress and the observation of parameter recovery in SiC MOSFET by stress superposition

Abstract In this study we examined the effects of room temperature DC and AC electrical stress on Si and SiC n-channel metal-oxide-semiconductor field effect transistors (MOSFETs). Measurement of threshold voltage, transconductance, subthreshold swing, charge pumping, and gate oxide breakdown are used to compare the impact of stress on Si MOSFETs and SiC MOSFETS, as well as to understand the processes of carrier injection and trapping at oxide and interface defects. DC stress is observed to promote negative charge buildup in the gate oxide and interface in Si MOSFETs. However, in SiC MOSFETs the net charge buildup sign alternates between negative and positive as the DC stress polarity is changed from positive to negative, respectively. This change of charge buildup sign explains our observation that degradation in SiC MOSFETs subjected to AC bipolar stress is insignificantly small, whereas AC stressing of Si MOSFETs is observed to be much more severe. Also, the superposition of alternating DC stress polarity eliminates the stress induced degradation in SiC MOSFETs thus enabling a simple process for parameter reconfiguration and recovery.

Synaptic Characteristics of Fully Depleted Silicon‐on‐Insulator Metal‐Oxide‐Semiconductor Field‐Effect Transistors and Synapse‐Neuron Arrayed Neuromorphic Hardware System

A fully depleted silicon‐on‐insulator (FDSOI) metal‐oxide‐semiconductor field‐effect transistors (MOSFETs) device is investigated as for an electronic synapse emulating the synaptic functions of the human brain with stable characteristics. Gate‐last processed FDSOI MOSFET with a high‐k/metal gate stack features a memory window of 103. Synaptic conductance is stably regulated by utilizing the FDSOI MOSFET, which offers the advantage of mitigating leakage current when compared to bulk Si MOSFET. Short‐ and long‐term plasticity are investigated by applying engineered pulse, verifying the long‐term synaptic properties of pattern recognition processes. With controllable synaptic conductance, the trade‐off between conductance change and linearity regarding the recognition rate is evaluated, attaining a recognition rate of 0.83. To verify the pre‐ and post‐synaptic weights within a real hardware‐based neuromorphic system, 5 × 6 FDSOI field‐effect transistor (FET) synapse array is interconnected to 10 × 10 leaky integrate‐and‐fire (LIF) neuron array. The synaptic plasticity of FDSOI MOSFET in post‐neurons following neuron firing in the neuron device is successfully demonstrated. These results indicate that FDSOI MOSFET devices could be applicable as synapse devices due to controllability and capability to realize signal transmissions and self‐learning processes simultaneously and used to mimic a synapse neuron network system by configuring a hardware system interconnected with the LIF neuron.

Compact Spice Models for Terafets

Field effect transistors (FETs) in plasmonic regimes of operation could detect terahertz (THz) radiation and operate as THz interferometers, spectrometers, frequency-to-digital converters and THz modulators and sources. We report on the development of compact models for Si MOS (Metal-Oxide-semiconductor) and heterostructure-based plasmonic FETs (or TeraFETs) suitable for circuit design in the THz range and based on the multi-segment unified charge control model. This model accounts for the electron inertia effect (by incorporating segmented Drude inductances), for the ballistic field effect mobility, which is proportional to the channel length, for parasitic resistances and capacitances and for the leakage current. It is validated by comparison with experimental data and TCAD simulation results. The model can be used for simulation and optimization of sub-THz and THz detectors. Our simulations use up to 200 segments in the device channel. The results are also in good qualitative agreement with the hydrodynamic simulations. Applications of our model could dramatically reduce astronomical design costs of nanoscale VLSI reaching US$1.5 billion for the 3 nm technological node.

Design and Comparative Analysis of an Ultra-Highly Efficient, Compact Half-Bridge LLC Resonant GaN Converter for Low-Power Applications

For low-power applications, this paper presents the development and design of a compact and ultra-highly efficient half-bridge LLC resonant converter. By using Galium Nitride (GaN) devices and high-efficient magnetics, the efficiency and power density of resonant converters can be improved. Compared to Silicon MOSFETs, GaN high-electron-mobility transistors (GaN HEMT) have a lower output capacitance and gate charge, resulting in lower driving loss and shorter dead times. Consequently, the proposed LLC converter based on GaN devices has excellent performance characteristics such as ultra-high efficiency, low switching losses, compact size, high voltage endurance, high operating temperature and high operating frequency. Furthermore, the proposed resonant converter features soft switching properties that ensure that the switches and diodes on the primary side are always switched at zero voltage and current. By doing so, LLC resonant converter switching losses are significantly reduced by up to 3.1%, and an overall efficiency of 98.5% is achieved. The LLC resonant converter design with GaN HEMT has great advantages over Si MOSFET solution regarding efficiency, overall losses, switching loose and power factor correction. A 240 W, 240 V to 60 V half-bridge GaN HEMT LLC resonant converter is simulated with a switching frequency of 75 KHz, along with the comparative analysis of the Si metal oxide semiconductor field effect transistor (MOSFET) solution. Moreover, the design and analysis of highly efficient magnetics with a power factor of 0.99 at full load is presented. A 240-Watt single stage LED driver with power factor correction is also designed to verify and compare the performance of proposed LLC resonant converter.

Thermomechanical Oriented Reliability Enhancement of Si MOSFET Panel-Level Packaging Fusing Ant Colony Optimization With Backpropagation Neural Network

Considerable advancements in power semiconductor devices have resulted in such devices being increasingly adopted in applications of energy generation, conversion, and transmission. Hence, we proposed a Fan-Out Panel-Level Packaging (FOPLP) design for 30V Si based Metal Oxide Semiconductor Field Effect Transistor (MOSFET). To achieve superior reliability of the packaging, we applied the Nondominated Sorting Genetic Algorithm with elitist strategy (NSGA-II) and Ant Colony Optimization–Backpropagation Neural Network (ACO–BPNN) to optimize the design of redistribution layer (RDL) in FOPLP. We first quantified the thermal resistance and thermo-mechanical coupling stress of the designed package under thermal cycling loading. Next, NSGA-II and ACO–BPNN were used to optimize the size of the RDL blind via. Finally, the effectiveness of the proposed reliability optimization methods was verified by performing thermal shock reliability ageing tests on the prepared devices.

Design and Implementation of a Paralleled Discrete SiC MOSFET Half-Bridge Circuit with an Improved Symmetric Layout and Unique Laminated Busbar

Silicon carbide (SiC) metal oxide semiconductor field effect transistors (MOSFETs) have many advantages compared to silicon (Si) MOSFETs: low drain-source resistance, high thermal conductivity, low leakage current, and high switching frequency. As a result, Si MOSFETs are replaced with SiC MOSFETs in many industrial applications. However, there are still not as many SiC modules to customize for each application. To meet the high-power requirement for custom applications, paralleling discrete SiC MOSFETs is an essential solution. However, it comes with many technical challenges; inequality in current sharing, different switching losses, different transient characteristics, and so forth. In this paper, the detailed MATLAB®/Simulink® Simpscape model of the SiC MOSFET from the datasheet and the simulation of the half-bridge circuit are investigated. Furthermore, this paper proposes the implementation of the four-paralleled SiC MOSFET half-bridge circuit with an improved symmetric gate driver layout. Moreover, a unique laminated busbar connected directly to the printed circuit board (PCB) is proposed to increase current and thermal capacity and decrease parasitic effects. Finally, the experimental and simulation results are presented using a 650 V SiC MOSFET (CREE) double-pulse test (DPT) circuit. The voltage overshoot problems and applied solutions are also presented.

The cascode configuration of a GaN static induction transistor for MHz power switch applications

A cascoded gallium nitride (GaN) static induction transistor (SIT) that combines a low-voltage Si metal-oxide-semiconductor field-effect transistor (MOSFET) at the input and a high-voltage GaN SIT at the output has been simulated and evaluated. The Schottky-gate SIT is an ideal choice for the cascode configuration as it provides a parallel Schottky diode, enabling bi-directional conduction. Simulation results show that the device has great potential for MHz frequency switching applications. Additionally, power losses in the Si MOSFET and GaN SIT have been analyzed separately.

Cryogenic Performances Comparisons Among Si MOSFET, SiC MOSFET, Cascode GaN, and GaN Devices

Cryogenic power electronics is an emerging technology to achieve high efficiency and high power density. As the key element of the power electronics system, the device performance should be evaluated under cryogenic temperatures. To demonstrate the differences between different materials and technologies, cryogenic temperature performance comparisons among silicon (Si) metal–oxide–semiconductor field-effect transistor (MOSFET), Si insulated-gate bipolar transistor (IGBT), silicon carbide (SiC) MOSFET, Cascode gallium nitride (GaN), and GaN high-electron-mobility transistor (HEMT) from different perspectives are made, which includes on-state resistance, threshold voltage, turn-on and turn-off times, turn-on and turn-off switching losses. The normalized values are adopted and results are drawn in the same pictures to demonstrate the differences. The results demonstrate that traditional Si devices have better performances under low temperatures. The SiC MOSFET is not suitable for cryogenic applications due to its increased on-state resistance and switching loss. Cascode GaN and GaN HEMT are promising candidates for cryogenic applications with reduced conduction loss and switching loss.

Optimization of Sacrificial Layer Etching in Single-Crystal Silicon Nano-Films Transfer Printing for Heterogeneous Integration Application.

As one of the important technologies in the field of heterogeneous integration, transfer technology has broad application prospects and unique technical advantages. This transfer technology includes the wet chemical etching of a sacrificial layer, such that silicon nano-film devices are released from the donor substrate and can be transferred. However, in the process of wet etching the SiO2 sacrificial layer present underneath the single-crystal silicon nano-film by using the transfer technology, the etching is often incomplete, which seriously affects the efficiency and quality of the transfer and makes the device preparation impossible. This article analyzes the principle of incomplete etching, and compares the four factors that affect the etching process, including the size of Si nano-film on top of the sacrificial layer, the location of the anchor point, the shape of Si nano-film on top of the sacrificial layer, and the thickness of the sacrificial layer. Finally, the etching conditions are obtained to avoid the phenomenon of incomplete etching of the sacrificial layer, so that the transfer technology can be better applied in the field of heterogeneous integration. Additionally, Si MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors) on sapphire substrate were fabricated by using the optimized transfer technology.

Current-to-transconductance ratio technique for simultaneous extraction of threshold voltage and parasitic resistances in MOSFETs

In this work, a current-to-transconductance ratio technique is proposed for simultaneous extraction of the threshold voltage (VT) and parasitic source (RS) and drain (RD) resistances in short channel metal–oxide–semiconductor field-effect transistors (MOSFETs). The proposed technique allows simultaneous extraction of RS, RD, and VT in any single MOSFET with the channel length modulation (CLM) and the structural asymmetry. The proposed method is experimentally verified through Si MOSFETs with intentional asymmetry by connecting an external resistor (Rext) to the source terminal. We experimentally confirmed that extracted RS, RD, and VT are independent of the drain bias (VDS) and intentional Rext employed for the asymmetry. We also compared the results with previously reported techniques.

C–Si bonded two-dimensional hole gas diamond MOSFET with normally-off operation and wide temperature range stability

A C–Si bonded SiO2/diamond interface is formed under a SiO2 mask during the selective diamond growth at a high temperature in a H2 atmosphere including methane (5%). A few monolayers with C–Si bonding at the SiO2/diamond surface are confirmed through X-ray photoelectron spectroscopy at the C1s and Si2p core levels from 290 eV to 271 eV and 107 eV–95 eV, respectively. In addition, secondary ion mass spectroscopy results suggest that the C–Si bonds, and not C–H bonds, are majority at the interface and are mainly responsible for the field effect transistor (FET) operation. Two-dimensional hole gas C–Si diamond metal–oxide–semiconductor FET (MOSFETs) are fabricated using the C–Si diamond sub-surface as a p-channel. The MOSFETs in which the actual length from the source to the drain (LSD) is 12 μm–6 μm show appreciable field-effect mobility (e.g. 140 cm2V−1s−1 at LSD = 12 μm and 300 K) and normally-off operation. The wide temperature characteristics of the C–Si MOSFETs are confirmed and the device shows high stability, and a high on/off ratio of 106 is maintained at 673 K. The C–Si bonding at the SiO2/diamond interface provide a lower interface state density which makes the MOSFET show high drain current density and field-effect mobility with normally-off operation.

Review on Driving Circuits for Wide-Bandgap Semiconductor Switching Devices for Mid- to High-Power Applications.

Wide-bandgap (WBG) material-based switching devices such as gallium nitride (GaN) high electron mobility transistors (HEMTs) and silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) are considered very promising candidates for replacing conventional silicon (Si) MOSFETs for various advanced power conversion applications, mainly because of their capabilities of higher switching frequencies with less switching and conduction losses. However, to make the most of their advantages, it is crucial to understand the intrinsic differences between WBG- and Si-based switching devices and investigate effective means to safely, efficiently, and reliably utilize the WBG devices. This paper aims to provide engineers in the power engineering field a comprehensive understanding of WBG switching devices’ driving requirements, especially for mid- to high-power applications. First, the characteristics and operating principles of WBG switching devices and their commercial products within specific voltage ranges are explored. Next, considerations regarding the design of driving circuits for WBG switching devices are addressed, and commercial drivers designed for WBG switching devices are explored. Lastly, a review on typical papers concerning driving technologies for WBG switching devices in mid- to high-power applications is presented.

Low-Frequency Noise Assessment of Vertically Stacked Si n-Channel Nanosheet FETs With Different Metal Gates

This article presents a comparative low-frequency noise (LFN) characterization of gate-all-around nanosheet n-channel Si metal–oxide–semiconductor field effect transistors, processed with three different metal gates (MGs): an aluminum-based reference process and two alternative effective work function (EWF) stacks. In all cases, the gate dielectric is composed of HfO2 over an SiO2 interfacial layer. The LFN figures of merit are extracted, such as the oxide trap density and Coulomb scattering coefficient, and the correlations with the threshold voltage and the electron mobility are investigated. Carrier number fluctuations are confirmed as the dominant mechanism of the 1/ ${f}$ noise for all evaluated devices. Additionally, it is shown that the specific MG can contribute to the carrier scattering, degrading the electron mobility. The most promising results are obtained for one of the alternative MGs, exhibiting a low oxide trap density level, a low threshold voltage and insignificant mobility degradation.

Novel driver circuit for switching performance improvements in SiC MOSFETs

Silicon carbide (SiC) metal–oxide–semiconductor field-effect transistors (MOSFETs) are expected to be an attractive replacement for Si MOSFETs in high power applications due to their high blocking voltage, high switching speed, and low switching losses. However, a high switching speed can lead to voltage and current overshoot as well as oscillation during the switching process, which results in additional losses and severe electromagnetic interference. It can also exceed the limit of the SiC MOSFET and cause irreversible damage to the device. Based on an analysis of the SiC MOSFET switching process voltage and current overshoot and oscillation generation mechanism, a voltage-injected active gate driver (AGD) was proposed. The proposed AGD can suppress the voltage and current overshoot and oscillation by injecting voltage into the gate of the SiC MOSFET during specific switching stages. Experimental results show that when compared with the conventional gate driver (CGD), the proposed AGD can suppress the voltage and current overshoot peaks by 16% and 12%, while reducing voltage and current oscillation times by 58% and 31%, respectively.

Comparison of the Effects of Nonlinearities for Si MOSFET and GaN E-HEMT Based VSIs

Nonlinearities in voltage source inverters (VSIs) such as; dead time, switching time, delay time, voltage drops on the power switches, parasitic capacitance, etc., are considered to be the main sources of the output voltage distortions. These distortions result in low-order harmonics in the output current, which in turn increase core losses and create torque ripples. In particular, for low-speed applications with low-inductance motors, the control performance and the stability of the system degrades substantially, especially when the system operates in the low-torque region. In this work, the effects of these nonlinearities on the phase current and on the current control of the silicon (Si) metal oxide semiconductor field effect transistor (MOSFET) based VSI are investigated with an air cored low inductance permanent magnet synchronous motor. Furthermore, Gallium nitride (GaN) enhancement mode high electron mobility transistor (E-HEMT) based VSI is proposed to overcome this problem. Next, improvements in the current control process are demonstrated by comparing the experimental results obtained by using GaN E-HEMT and Si MOSFET based VSIs. Results show that GaN E-HEMT based VSI is a better choice for applications, which require a high bandwidth control.

A Comparison between Si and SiC MOSFETs

The Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) has developed quickly and become one of the most important devices for a wide range of applications. There is an increasing need for power MOSFET devices with low power consumption and high energy efficiency. Silicon (Si) and Silicon Carbide (SiC) are two kinds of materials used in power MOSFET devices, which have their own advantages of performance for each use. This paper makes a comparison of the on-resistance and high-temperature performance between Si and SiC MOSFETs. The analysis of the differences between the two will mainly come out from the perspective of material properties, and the conclusion of what is the ideal material for power MOSFET devices will be finally drawn.

Comparative efficiency analysis for silicon, silicon carbide MOSFETs and IGBT device for DC–DC boost converter

In present study, a comparative efficiency analysis for silicon (Si), silicon carbide (SiC) metal oxide semiconductor field effect transistors (MOSFETs) and insulated gate bipolar transistor (IGBT) device based DC–DC boost converter is performed. Due to different gate-drive characteristics of power semiconductor devices such as Si, SiC MOSFETs and IGBT device, different voltage levels are required to drive aforementioned devices. A 500 W boost converter for wide input voltage range (30–72 V) and 110 V output voltage is designed having a single gate driver circuit for Si, SiC MOSFETs and IGBT. A single gate driver provides the gate-source (or base-emitter in case of IGBT) signal for all the devices which eliminates the use of separate gate driver circuit. Si MOSFET and IGBT are driven by 12 V gate-source voltage whereas SiC MOSFET is operated by 18 V gate-source voltage using the gate driver circuit. An experimental study is performed for the comparative efficiency analysis for Si, SiC MOSFETs and IGBT device based converter for 20 and 50 kHz switching frequencies. It is found that SiC based converter provides highest efficiency ≈ 97.8%, whereas the lowest efficiency ≈ 94% is found for IGBT based converter at 20 kHz switching frequency. SiC based converter gives higher efficiency because lower conduction loss owning to lower on-state resistance as compared to Si MOSFET. Besides this, SiC application has another advantage such as low switching loss at higher frequency resulting compact size of converter. However, use of IGBT at higher switching frequency results in higher switching losses, hence lower efficiency of the converter.

A Digital-Controlled SiC-Based Solid State Circuit Breaker with Soft Switch-Off Method for DC Power System

Due to the lower on-state resistance, direct current (DC) solid state circuit breakers (SSCBs) based on silicon-carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) can reduce on-state losses and the investment of the cooling system when compared to breakers based on silicon (Si) MOSFETs. However, SiC MOSFETs, with smaller die area and higher current density, lead to weaker short-circuit ability, shorter short-circuit withstand time and higher protection requirements. To improve the reliability and short-circuit capability of SiC-based DC solid state circuit breakers, the short-circuit fault mechanisms of Si MOSFETs and SiC MOSFETs are revealed. Combined with the desaturation detection (DESAT), a “soft turn-off” short-circuit protection method based on source parasitic inductor is proposed. When the DESAT protection is activated, the “soft turn-off” method can protect the MOSFET against short-circuit and overcurrent. The proposed SSCB, combined with the flexibility of the DSP, has the μs-scale ultrafast response time to overcurrent detection. Finally, the effectiveness of the proposed method is validated by the experimental platform. The method can reduce the voltage stress of the power device, and it can also suppress the short-circuit current.

Theoretical analysis and optimization of high-k dielectric layers for designing high-performance and low-power-dissipation nanoscale double-gate MOSFETs

The carrier transport and tunneling mechanisms in nanoscale double-gate metal–oxide–semiconductor field-effect transistors (MOSFETs) with different dielectric layers is investigated using a simple two-dimensional analytical model, revealing good agreement with drift–diffusion and hydrodynamic models at lower gate voltages. The model is utilized to optimize the MOSFET performance by minimizing the carrier leakage and improving the gate control on the carrier transport through the channel, which can be determined by the gate-to-drain capacitance ratio. It is well known that thicker physical layers of high-k dielectrics can be used to reduce the gate tunneling current without compromising the gate controllability over the channel conduction, by providing the same equivalent oxide thickness as SiO2. However, use of a dielectric layer with a lower conduction-band offset (CBO) in a Si MOSFET can result in appreciable tunneling through the gate, as shown in our computational results for the TiO2 layer. In this study, we obtain an optimized thickness of 10 A for the La2O3 dielectric layer, which results in a minimum leakage current via tunneling and a maximum gate-to-drain capacitance ratio due to its high dielectric constant and CBO. Such devices could be applicable in analog amplifier circuits due to their high intrinsic gain and lower “on” and “off” static power dissipation. The analysis of this device in a digital circuit also shows a higher Ion/Ioff ratio with the least drain-induced barrier lowering effect. The results of this study thus predict the suitability of this MOSFET for use in low-power devices and logic circuits.

Analysis of electron transport in the nano-scaled Si, SOI and III-V MOSFETs: Si/SiO2 interface charges and quantum mechanical effects

The ITRS predicts that the scaling of planar CMOS (Complementary Metal Oxide Semiconductor) technology will continue till the 22 nm technology node [1] and a possible extension beyond is appealing [2]. In this work, we investigate the effect of electron confinement [3] in nanoscaled transistor channels of 25 nm surface channel Si and 32 nm SOI (Silicon on Insulator) and 15 nm IF (Implant Free) III-V MOSFETs using a self-consistent solution of 1 D Poisson - Schrödinger equation [4,5]. For simulat ion and development with accuracy of nano-scaled of 25 nm gate length Si MOSFET (Metal Oxide Semiconductor Field Effect Transistor), 32 nm SOI Implant Free (IF) MOSFET, and 15nm Implant Free III-V MOSFET transistors, we investigated the bandstructure and quantum confinement effects occurring near the oxide-semiconductor interface inmetal-Oxide-Semiconductor (MOS) structure of Si MOSFET device. These investigation have been carried out using a selfconsistent solution of 1D Poisson-Schrödinger equation across the channel of conventional Si / SOI / III-V MOSFET Transistors. To solve self-consistently 1D Poisson-Schrödinger equations across the channel of a conventional Si, SOI, and an Implant Free III-V MOSFETs to determine the conduction and valence band profiles, electron density, electron sheet density, eigenstate and eigenfunctions in these structures. We present the simulat ion results of conduction band profile, electron density (classical and quantum mechanical), eigenstate and eigenfunctions for Si, SOI and III-V MOSFET structures at two different bias voltages of 0.5 V and 1.0 V. For comparison, we calculate the electron sheet density (quantum mechanically) as a function of the applied gate voltages.