Abstract
Considerable advancements in power semiconductor devices have resulted in such devices being increasingly adopted in applications of energy generation, conversion, and transmission. Hence, we proposed a Fan-Out Panel-Level Packaging (FOPLP) design for 30V Si based Metal Oxide Semiconductor Field Effect Transistor (MOSFET). To achieve superior reliability of the packaging, we applied the Nondominated Sorting Genetic Algorithm with elitist strategy (NSGA-II) and Ant Colony Optimization–Backpropagation Neural Network (ACO–BPNN) to optimize the design of redistribution layer (RDL) in FOPLP. We first quantified the thermal resistance and thermo-mechanical coupling stress of the designed package under thermal cycling loading. Next, NSGA-II and ACO–BPNN were used to optimize the size of the RDL blind via. Finally, the effectiveness of the proposed reliability optimization methods was verified by performing thermal shock reliability ageing tests on the prepared devices.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
More From: IEEE Transactions on Components, Packaging and Manufacturing Technology
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.