Si Metal-oxide-semiconductor Field-effect Transistors Research Articles

Theoretical analysis and optimization of high-k dielectric layers for designing high-performance and low-power-dissipation nanoscale double-gate MOSFETs

The carrier transport and tunneling mechanisms in nanoscale double-gate metal–oxide–semiconductor field-effect transistors (MOSFETs) with different dielectric layers is investigated using a simple two-dimensional analytical model, revealing good agreement with drift–diffusion and hydrodynamic models at lower gate voltages. The model is utilized to optimize the MOSFET performance by minimizing the carrier leakage and improving the gate control on the carrier transport through the channel, which can be determined by the gate-to-drain capacitance ratio. It is well known that thicker physical layers of high-k dielectrics can be used to reduce the gate tunneling current without compromising the gate controllability over the channel conduction, by providing the same equivalent oxide thickness as SiO2. However, use of a dielectric layer with a lower conduction-band offset (CBO) in a Si MOSFET can result in appreciable tunneling through the gate, as shown in our computational results for the TiO2 layer. In this study, we obtain an optimized thickness of 10 A for the La2O3 dielectric layer, which results in a minimum leakage current via tunneling and a maximum gate-to-drain capacitance ratio due to its high dielectric constant and CBO. Such devices could be applicable in analog amplifier circuits due to their high intrinsic gain and lower “on” and “off” static power dissipation. The analysis of this device in a digital circuit also shows a higher Ion/Ioff ratio with the least drain-induced barrier lowering effect. The results of this study thus predict the suitability of this MOSFET for use in low-power devices and logic circuits.

Analysis of electron transport in the nano-scaled Si, SOI and III-V MOSFETs: Si/SiO2 interface charges and quantum mechanical effects

The ITRS predicts that the scaling of planar CMOS (Complementary Metal Oxide Semiconductor) technology will continue till the 22 nm technology node [1] and a possible extension beyond is appealing [2]. In this work, we investigate the effect of electron confinement [3] in nanoscaled transistor channels of 25 nm surface channel Si and 32 nm SOI (Silicon on Insulator) and 15 nm IF (Implant Free) III-V MOSFETs using a self-consistent solution of 1 D Poisson - Schrödinger equation [4,5]. For simulat ion and development with accuracy of nano-scaled of 25 nm gate length Si MOSFET (Metal Oxide Semiconductor Field Effect Transistor), 32 nm SOI Implant Free (IF) MOSFET, and 15nm Implant Free III-V MOSFET transistors, we investigated the bandstructure and quantum confinement effects occurring near the oxide-semiconductor interface inmetal-Oxide-Semiconductor (MOS) structure of Si MOSFET device. These investigation have been carried out using a selfconsistent solution of 1D Poisson-Schrödinger equation across the channel of conventional Si / SOI / III-V MOSFET Transistors. To solve self-consistently 1D Poisson-Schrödinger equations across the channel of a conventional Si, SOI, and an Implant Free III-V MOSFETs to determine the conduction and valence band profiles, electron density, electron sheet density, eigenstate and eigenfunctions in these structures. We present the simulat ion results of conduction band profile, electron density (classical and quantum mechanical), eigenstate and eigenfunctions for Si, SOI and III-V MOSFET structures at two different bias voltages of 0.5 V and 1.0 V. For comparison, we calculate the electron sheet density (quantum mechanically) as a function of the applied gate voltages.

Progress of the study on carrier scattering mechanisms of silicon/germanium field effect transistors

As the feature size of Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) continues to decrease, large numbers of new problems appear. Techniques such as strain project, new channel materials and new device structures are considered by academics and industry to be effective ways to continue to improve device performance. In this paper, the scattering mechanism of carriers in the device channel is studied from three aspects: strain technique, new channel material and new structure device: (1) strain technique: Biaxial tensile strain can change carrier distribution among different energy levels, which affects Coulomb scattering and Coulomb mobility. Furthermore, from the TEM image, it is found that biaxial tensile reduces the channel surface roughness for Si nMOSFET, leading an enhancement of electron mobility. However, no such similar phenomena were observed in pMOSFET. Based on this, a new method for calculating the mobility of MOSFET surface roughness scattering using TEM image has been proposed. (2) New channel material: In the germanium (Ge) transistors with different crystal faces, the scattering mechanisms of electron under high field conditions are different. The phonon scattering dominates the Ge(100) transistor, while the surface roughness scattering dominates the Ge(110), (111) transistors. This result is quite different from Si MOSFET. Therefore, a unified model for the scattering mechanism of electron in Ge nMOSFET has been proposed. In SiGe transistors, alloy scattering mainly play a role in the region with relatively small effective electric field (<i>E</i><sub>eff</sub>). The strength of alloy scattering would be weakened in high field and could be decreased by reducing the thickness of SiGe layer. (3) New structure devices: In ultra-thin body germanium (GeOI) transistors, carrier transport is influenced by high- k /channel interfaces, as well as Ge channel/buried oxide (BOX) interface. As the Ge layer thickness decreases, carrier distribution is closer to the interfaces, which intensifies Coulomb scattering and surface roughness scattering. As a result, the mobility in GeOI transistor decreases as the thickness scaling. In addition, the distribution of electron in different energy valleys changes with the thickness decrease in Ge layer, which affects the scattering of electrons. When the Ge film is lower than 10 nm, a part of electron in the L valley will move to the Γ valley, causing the decrease of electron effective mass and increasing the electron mobility.

Fast Cerebrospinal Fluid Detection Using Inexpensive Modular Packaging with Disposable Testing Strips

This report details the use of a Si Metal Oxide Semiconductor Field Effect Transistor (MOSFET) with the gate connected to a disposable antibody-functionalized electrode for the detection of β-2-transferrin (β2T) as a marker of cerebral spinal fluid (CSF). Through the design of a Si based PCB the need for GaN High Electron Mobility Transistors has been mitigated and brings the cost of production for commercial application closer to realization. Through the use of a double pulse method to the test electrode and the drain of the Si MOSFET, ionicity of the test solution is no longer a concern as a double layer is produced and perturbed on the test electrode giving rise to current changes related to the concentration of the biomarker. Additionally, the PCB provides connections for an oscilloscope readout or an onboard display entirely removing the need for any expensive semiconductor parameter analyzers. Clinically, the cutoff for β2T as indicator of CSF leakage has traditionally been limited to ∼2 μg/mL and takes several hours; with this newly designed board, CSF was detected at levels from 0.1 ng/mL to 100 μg/mL within 5 minutes, greatly improving the detection limits and feedback time for medical professionals.

New Reentrant Insulating Phases in Strongly Interacting 2D Systems with Low Disorder

The metal-insulator transition (MIT) in two-dimension (2D) was discovered by Kravchenko et al. more than two decades ago in strongly interacting 2D electrons residing in a Si-metal-oxide-semiconductor field-effect transistor (Si-MOSFET). Its origin remains unresolved. Recently, low magnetic field reentrant insulating phases (RIPs), which dwell between the zero-field (B = 0) metallic state and the integer quantum Hall (QH) states where the Landau-level filling factor υ > 1, have been observed in strongly correlated 2D GaAs hole systems with a large interaction parameter, rs, (~20–40) and a high purity. A new complex phase diagram was proposed, which includes zero-field MIT, low magnetic field RIPs, integer QH states, fractional QH states, high field RIPs and insulating phases (HFIPs) with υ < 1 in which the insulating phases are explained by the formation of a Wigner crystal. Furthermore, evidence of new intermediate phases was reported. This review article serves the purpose of summarizing those recent experimental findings and theoretical endeavors to foster future research efforts.

Threshold voltage peculiarities and bias temperature instabilities of SiC MOSFETs

Silicon carbide (SiC) based metal-oxide semiconductor-field-effect-transistors (MOSFETs) are increasingly entering the high power device market. Besides all the well-known benefits which come along with these new generations of switches, the nature of the wide bandgap material and the different properties of the semiconductor-dielectric interface involve some natural peculiarities in threshold voltage variation and bias-temperature-instability (BTI) which differ from comparable silicon (Si) MOSFET counterparts and which need to be understood and assessed. The target of this paper is to highlight such differences, explain their relation to the semiconductor material, challenge their relevance for the application and define their consequences with regard to datasheet specifications. Most of the new effects can be understood by means of simple physical models and do not compromise the reliability of the device. However, it turns out that the standard test procedures typically used to characterize threshold voltage and threshold voltage drifts for Si devices need to be adapted for SiC MOSFETs. A new measure-stress-measure procedure for BTI evaluation of SiC MOSFETs is proposed which allows distinguishing between reversible threshold voltage hysteresis and more permanent threshold voltage drift (BTI). The measurement pattern is then used to assess the VTH stability of recently launched SiC MOSFET parts. The tested devices differ considerably in BTI drift amplitude and drift variation. The differences are attributed to variations in device processing and device design.

(Invited) Investigation of Critical Interfaces in Few-Layer MoS2 Field Effect Transistors with High-k Dielectrics

Transition metal dichalcogenides (TMDs) as 2D or few-layer semiconducting channel material are being widely studied to lower power consumption and obtain negligible short channel effects with continued transistor scaling [1-4]. Meanwhile, research needs to be conducted on top-gated, metal-oxide-semiconductor field effect transistors (MOSFETs) to correctly assess the possibility of TMDs supplanting silicon in the channel region. This is because top-gate device architectures face some key integration challenges that typical bottom-gate TMD FET structures do not experience. As an example, molybdenum disulfide (MoS2) is supposed to have no dangling interfacial bonds, making it difficult to form high-k dielectrics on them. Therefore, surface functionalization of TMDs has attracted attention [5-12]. However, detailed understanding on performance of transistors with metal/high-k/TMD top-gate stacks are still lacking. In addition, a major hurdle of incorporating these two-dimensional (2D) materials in device structures of any kind is the high contact resistance at the metal/TMD interface [13-15]. Recent results have shown that the backside dielectric can influence top-gate MOSFET performance [16]. In this work, few-layer MoS2 FET-based devices were fabricated using top and bottom high-k dielectrics (Al2O3 and/or HfO2). The C-V response of a top-gate, HfO2/MoS2 gate stack on a backside SiO2 layer demonstrated the existence of specific defects at the interface, which demonstrated frequency dependent “humps” in depletion – similar to conventional Si MOSFETs with unpassivated silicon dangling bonds in the dielectric/Si interfacial region. Also, a comparison of UHV and HV metal deposition on MoS2 as contacts for source and drain was done where results demonstrated that UHV deposited metals were superior to HV ones. In an additional experiment with Al2O3 as the bottom-gate dielectric layer, the intrinsic mobility and subthreshold slope were greatly improved compared to SiO2 or HfO2 as back gate dielectric FETs, indicating a positive influence on top-gate device performance even without any backside bias. Furthermore, a forming gas anneal is found to further enhance device performance due to a reduction in charge trap density at dielectric interfacial regions, and improved metal contact formation. Another significant finding in top-gate FET performance is the high-k dielectric screening effect of the backside Al2O3 layer. Results demonstrate that the extracted top-gate field effect mobility values are higher compared to SiO2 or HfO2 as a backside oxide – even though all FETs have the same top-side HfO2 dielectric oxide and no back bias. Acknowledgement – This work was supported in part by the US/Ireland R&D Partnership (UNITE) under the NSF award ECCS-1407765, Science Foundation Ireland under the US-Ireland R&D Partnership Programme Grant Number SFI/13/US/I2862, and the center for Low Energy Systems Technology (LEAST), one of six SRC STARnet Centers, sponsored by MARCO and DARPA.

Performance enhancement of CMOS terahertz detector by drain current**Project supported by the National Key R&D Program of China (Grant No. 2016YFB-0402403), the Natural Science Foundation of Jiangsu Province, China (Grant No. BK20141321), CAST Project, China (Grant No. 08201601), and the National Science Foundation for Young Scholars of China (Grant No. 61404072).

In this paper, we study the effect of the drain current on terahertz detection for Si metal-oxide semiconductor field-effect transistors (MOSFETs) both theoretically and experimentally. The analytical model, which is based on the small-signal equivalent circuit of MOSFETs, predicts the significant improvement of the voltage responsivity Rv with the bias current. The experiment on antennas integrated with MOSFETs agrees with the analytical model, but the Rv improvement is accompanied first by a decrease, then an increase of the low-noise equivalent power (NEP) with the applied current. We determine the tradeoff between the low-NEP and high-Rv for the current-biased detectors. As the best-case scenario, we obtained an improvement of about six times in Rv without the cost of a higher NEP. We conclude that the current supply scheme can provide high-quality signal amplification in practical CMOS terahertz detection.

Comparison between SiC- and Si-Based Inverters for Photovoltaic Power Generation Systems

100-W class power storage systems were developed, which comprised spherical Si solar cells, a maximum power point tracking charge control-ler, a lithium-ion battery, and one of two different types of direct current (DC)-alter- nating current (AC) converters. One inverter used SiC met-al-oxide-semicon-ductor field-effect transistors (MOSFETs) as switching devices while the other used Si MOSFETs. In these 100-W class inverters, the ON resistance was considered to have little influence on the efficiency. Nevertheless, the SiC-based inverter exhibited an approximately 3% higher DC-AC conversion efficiency than the Si-based inverter. Power loss analysis indicated that the higher efficiency resulted predominantly from lower switching and reverse recovery losses in the SiC MOSFETs compared with in the Si MOSFETs.

Graphene field-effect transistor application-electric band structure of graphene in transistor structure extracted from quantum capacitance

Recently, various two-dimensional (2D) materials, such as graphene, transition metal dichalcogenides and so on, have attracted much attention in electron device research. The most important characteristic of graphene is its highest mobility of all semiconductor channels at room temperature. However, it is obvious that more than a good mobility characteristic is required to realize the field effect transistor (FET), and intense arguments from various points of view are necessary. In this paper, the issues with Si-metal oxide semiconductor FETs (Si-MOSFET) and the advantage of 2D materials are discussed. The present state of graphene FETs with respect to gate stack formation and band gap engineering is reported. Moreover, based on the density of states (DOS) of graphene extracted using the quantum capacitance (CQ) measurement, it is shown that the electric band structure of graphene in contact with gate insulators or metal electrode deviates from its intrinsic band structure.

Inversion channel diamond metal-oxide-semiconductor field-effect transistor with normally off characteristics

We fabricated inversion channel diamond metal-oxide-semiconductor field-effect transistors (MOSFETs) with normally off characteristics. At present, Si MOSFETs and insulated gate bipolar transistors (IGBTs) with inversion channels are widely used because of their high controllability of electric power and high tolerance. Although a diamond semiconductor is considered to be a material with a strong potential for application in next-generation power devices, diamond MOSFETs with an inversion channel have not yet been reported. We precisely controlled the MOS interface for diamond by wet annealing and fabricated p-channel and planar-type MOSFETs with phosphorus-doped n-type body on diamond (111) substrate. The gate oxide of Al2O3 was deposited onto the n-type diamond body by atomic layer deposition at 300 °C. The drain current was controlled by the negative gate voltage, indicating that an inversion channel with a p-type character was formed at a high-quality n-type diamond body/Al2O3 interface. The maximum drain current density and the field-effect mobility of a diamond MOSFET with a gate electrode length of 5 μm were 1.6 mA/mm and 8.0 cm2/Vs, respectively, at room temperature.

Design of Parasitic Inductance Reduction in GaN Cascode FET for High-Efficiency Operation

This paper presents a method of parasitic inductance reduction for high-speed switching and high-efficiency operation of a cascode structure with a low-voltage enhancement-mode silicon (Si) metal–oxide–semiconductor field-effect transistor (MOSFET) and a high-voltage depletion-mode gallium nitride (GaN) field-effect transistor (FET). The method is proposed to add a bonding wire interconnected between the source electrode of the Si MOSFET and the gate electrode of the GaN FET in a conventional cascode structure package to reduce the most critical inductance, which provides the major switching loss for a high switching speed and high efficiency. From the measured results of the proposed and conventional GaN cascode FETs, the rising and falling times of the proposed GaN cascode FET were up to 3.4% and 8.0% faster than those of the conventional GaN cascode FET, respectively, under measurement conditions of 30 V and 5 A. During the rising and falling times, the energy losses of the proposed GaN cascode FET were up to 0.3% and 6.7% lower than those of the conventional GaN cascode FET, respectively.

Design of Parasitic Inductance Reduction in GaN Cascode FET for High Efficiency Operation

This paper presents a method of parasitic inductance reduction for high-speed switching and high-efficiency operation of a cascode structure with a low-voltage enhancement-mode silicon (Si) metal–oxide–semiconductor field-effect transistor (MOSFET) and a high-voltage depletion-mode gallium nitride (GaN) field-effect transistor (FET). The method is proposed to add a bonding wire interconnected between the source electrode of the Si MOSFET and the gate electrode of the GaN FET in a conventional cascode structure package to reduce the most critical inductance, which provides the major switching loss for a high switching speed and high efficiency. From the measured results of the proposed and conventional GaN cascode FETs, the rising and falling times of the proposed GaN cascode FET were up to 3.4% and 8.0% faster than those of the conventional GaN cascode FET, respectively, under measurement conditions of 30 V and 5 A. During the rising and falling times, the energy losses of the proposed GaN cascode FET were up to 0.3% and 6.7% lower than those of the conventional GaN cascode FET, respectively.

Two-dimensional models of threshold voltage and subthreshold current for symmetrical double-material double-gate strained Si MOSFETs**Project supported by the National Natural Science Foundation of China (Grant Nos. 61376099, 11235008, and 61205003).

The two-dimensional models for symmetrical double-material double-gate (DM-DG) strained Si (s-Si) metal–oxide semiconductor field effect transistors (MOSFETs) are presented. The surface potential and the surface electric field expressions have been obtained by solving Poisson’s equation. The models of threshold voltage and subthreshold current are obtained based on the surface potential expression. The surface potential and the surface electric field are compared with those of single-material double-gate (SM-DG) MOSFETs. The effects of different device parameters on the threshold voltage and the subthreshold current are demonstrated. The analytical models give deep insight into the device parameters design. The analytical results obtained from the proposed models show good matching with the simulation results using DESSIS.

A Gallium Nitride-Based Power Module for Totem-Pole Bridgeless Power Factor Correction Rectifier

The totem-pole bridgeless power factor correction (PFC) rectifier has recently gained popularity for ac-dc power conversion. The emerging gallium nitride (GaN) high-electron-mobility transistor (HEMT), having a small body diode reverse recovery effect and low switching loss, is a promising device for use in the totem-pole approach. The design, fabrication, and thermal analysis of a GaN-based full-bridge multi-chip module (MCM) for totem-pole bridgeless PFC rectifier are introduced in this work. Four cascode GaN devices using the same pair of high-voltage GaN HEMT and low-voltage silicon (Si) power metal-oxide-semiconductor field-effect transistor (MOSFET) chips, as used in the discrete TO-220 package, were integrated onto one aluminum nitride direct-bonded-copper (AlN-DBC) substrate in a newly designed MCM. This integrated power module achieves the same function as four discrete devices mounted on the circuit board. In this module design, the Si and GaN bare die were arranged in a stack-die format for each cascode device to eliminate the critical common source inductance, and thus to reduce parasitic ringing at turn-off transients. In addition, an extra capacitor was added in parallel with the drain-source terminals of the Si MOSFET in each cascode GaN device to compensate for the mismatched junction capacitance between the Si MOSFET and GaN HEMT, which could accomplish the internal zero-voltage switching of the GaN device and reduce its turn-on loss. The AlN-DBC substrate and the flip-chip format were also applied in the module design. This GaN-based MCM shows an improved heat dissipation capability based on the thermal analysis and comparison with the discrete GaN device. The totem-pole bridgeless PFC rectifier built using this integrated power module is expected to have a peak efficiency of higher than 99% with a projected power density greater than 400 W/in3.

Static and switching characteristics of 3.3 kV double channel-doped SiC vertical junction field effect transistor in cascode configuration

A silicon-carbide (SiC) junction field-effect transistor (JFET)/Si metal–oxide–semiconductor field-effect transistor (MOSFET) cascode is a good solution owing to its high reliability, low on-resistance, high switching speed, and good gate controllability. A 3.3 kV SiC vertical JFET using a double channel doping technique is proposed in this paper. The characteristics of a cascode including the developed JFET are also presented. A blocking voltage higher than 4.0 kV and a low on-resistance of 14.7 mΩ cm2 were realized. The saturation current of the cascode was suppressed by controlling the threshold voltage of the JFET. Moreover, small switching losses were obtained.

Practical implementation of a silicon carbide‐based 300 kHz, 1.2 kW hard‐switching boost‐converter and comparative thermal performance evaluation

Field experience shows that the vast majority of solar photovoltaic (PV) energy system failures are related to the power conditioning system (PCS). Among the principal reliability issues of PV PCSs are thermal management and heat extraction mechanisms. The study considers practical implementation of a DC–DC boost converter as a solar PV pre-regulator in terms of thermal management, with comparative thermal performance evaluations of silicon carbide (SiC) semiconductors and silicon (Si) metal-oxide-semiconductor field-effect transistors (MOSFETs). Thermal performance evaluation of power semiconductors is based on a 1.2 kW DC–DC converter with: (i) various switching frequencies up to 300 kHz, in steps of 25 kHz; (ii) case temperatures from 25 to 150°C; and (iii) a natural convection heatsink with temperature increase rate of 0.5°C/W. Simulation and experimental results verify that losses from SiC semiconductors are low compared with Si MOSFETs. This provides an opportunity for designing a pre-regulator DC–DC boost converter with less effort required for thermal management and enhanced reliability.

Nonlinear photoresponse of field effect transistors terahertz detectors at high irradiation intensities

Terahertz power dependence of the photoresponse of field effect transistors, operating at frequencies from 0.1 to 3 THz for incident radiation power density up to 100 kW/cm2 was studied for Si metal–oxide–semiconductor field-effect transistors and InGaAs high electron mobility transistors. The photoresponse increased linearly with increasing radiation intensity up to the kW/cm2 range. Nonlinearity followed by saturation of the photoresponse was observed for all investigated field effect transistors for intensities above several kW/cm2. The observed photoresponse nonlinearity is explained by nonlinearity and saturation of the transistor channel current. A theoretical model of terahertz field effect transistor photoresponse at high intensity was developed. The model explains quantitative experimental data both in linear and nonlinear regions. Our results show that dynamic range of field effect transistors is very high and can extend over more than six orders of magnitudes of power densities (from ∼0.5 mW/cm2 to ∼5 kW/cm2).

Channel length scaling limits of III–V channel MOSFETs governed by source–drain direct tunneling

The difference in the impact of source–drain (SD) direct tunneling in In0.53Ga0.47As and InP metal–oxide–semiconductor field-effect transistors (MOSFETs) was investigated by a quantum Wigner Monte Carlo simulation. It was found that the subthreshold current increase due to SD direct tunneling is more marked in In0.53Ga0.47As MOSFETs owing to their lower effective mass. In addition, the critical channel length at which a drastic increase in subthreshold current occurs owing to SD direct tunneling was found to be about 20 nm for both In0.53Ga0.47As and InP MOSFETs. Since this value is significantly larger than that for Si MOSFETs, SD direct tunneling can be a major obstacle in downscaling III–V MOSFETs into Lch < 20 nm. Hence, to go beyond the end of the roadmap, we will need a selection of materials to suppress SD direct tunneling.

A model of hot carrier gate current for uniaxially strained Si NMOSFET

Hot carrier gate current is one of the factors that influence the power and reliability of metal-oxide-semiconductor field effect transistor (MOSFET). Based on the physical process of generation of the hot carrier effect, a model of hot carrier gate current for uniaxially strained Si NMOSFET is developed. With that model, the simulation results of hot carrier gate current against stress intensity, gate-source bias, channel doping concentration, and drain-source bias are obtained and analyzed. The relationship between life time of time-dependent dielectric break down (TDDB) and gate-source bias is simulated and analyzed. Results show that the uniaxially strained Si MOSFET not only has smaller hot carrier gate current, but also has more stable reliability as compared with the strainless bulk device. Meanwhile, the simulation results match the experimental results very well, which validates the accuracy of the model.