Si Devices Research Articles

Evaluation of SiC-MOSFET by Repetitive UIS Tests for Solid State Circuit Breaker

This paper investigates a degradation of SiC power device for DC circuit breaker through repetitive unclamped inductive switching (UIS) tests. Being much lower compared with Si devices, it has been considered an application for DC circuit breakers using SiC semiconductor. In order to use for the DCbreaker, it is essential to evaluate the destructive endurance for UIS test.This paper evaluates a deterioration phenomenon by paying attention to the decrease of the gate voltage of the SiC-MOSFETs under the degradation at repetitive UIS test.

Accelerated Testing of SiC Power Devices under High-Field Operating Conditions

Power metal-oxide-semiconductor field-effect transistors (MOSFETs) experience conditions of high field during normal operation. During switching conditions, unexpected transient events may occur which force devices into avalanche or short circuit conditions. Moreover, silicon carbide devices typically experience higher fields in the gate oxide and drift regions than comparable Si devices due to channel and drift property differences. A summary of SiC MOSFET reliability and ruggedness test results are reported here. Reliability tests under high field conditions: positive-bias and negative-bias temperature instability (PBTI, NBTI) to examine threshold stability; time-dependent dielectric breakdown (TDDB) for gate oxide lifetime extrapolation; high-temperature reverse bias (HTRB); and HTRB testing under high neutron flux to determine terrestrial neutron single-event burnout (SEB) rates. High-power ruggedness evaluation is presented for SiC MOSFETs under forced avalanche conditions (unclamped inductive switching (UIS)) and under short-circuit operation to bound device safe operating areas. Overall results demonstrate the intrinsic reliability of SiC MOSFETs.

Evaluation of Interface Traps Type, Energy Level and Density of SiC MOSFETs by Means of C-V Curves TCAD Simulations

SiC MOSFETs are promising devices for many power applications. They are replacing Si devices due to the higher performance of SiC material. However, there are some technological issues still unsolved. One of the main problems is the high density of traps at the SiC/SiO2 interface. Traps distribution at such interface is complex and it affects the overall performance of the device. Traps influence both current-voltage and capacitance-voltage characteristics of a SiC MOSFET. The aim of this work is the study of interface traps effects on C-V and I-V curves for a 1200 V SiC MOSFET. The numerical study is adopted to explain the shape of experimental C-V curves of commercial devices.

Buffered Oxide Etchant Post-Treatment of a Silicon Nanofilm for Low-Cost and Performance-Enhanced Chemical Sensors.

The high surface-to-volume ratio of nanostructured materials is the key factor for excellent performance when applied to chemical sensors. In order to achieve this by a facile and low-cost fabrication strategy, buffered oxide etchant (BOE) treatment of a silicon (Si)-based sensor was proposed. An n+-n--n+ Si nanofilm structure was treated with a BOE, and palladium nanoparticles (PdNPs) were coated on the n-type Si channel surface via short-time electron beam evaporation to enable a highly sensitive and selective sensing of hydrogen (H2) gas. The BOE treatment effect on lightly doped n-type Si was investigated, and the surface morphology of the etched Si was analyzed. Furthermore, the H2 sensing characterization of PdNP-decorated Si devices with various BOE treatment times was systematically evaluated at room temperature. The results revealed that the surface of n-type Si is roughened by BOE treatment, which can further enhance the H2-sensing performance of Pd-decorated Si. The elaborate study on the BOE-post-treated Si H2 sensor showed that the performance enhancement was stable. The BOE treatment strategy was also applied to the nanopatterned Si sensors, which induced a clear performance enhancement for the H2 sensing.

Ultra-compact, High-Frequency Power Integrated Circuits Based on GaN-on-Si Schottky Barrier Diodes

Gallium nitride (GaN) transistors are being employed in an increasing number of applications thanks to their excellent performance and competitive price. Yet, GaN diodes are not commercially available, and little is known about their performance and potential impact on power circuit design. In this article, we demonstrate scaled-up GaN-on-Si Tri-Anode Schottky barrier diodes (SBDs), whose excellent dc and switching performance are compared to commercial Si fast-recovery diodes and SiC SBDs. Moreover, the advantageous lateral GaN-on-Si architecture enables the integration of several devices on the same chip, paving the way for power integrated circuits (ICs). This is demonstrated by realizing a diode-multiplier IC, which includes up to eight monolithically integrated SBDs on the same chip. The IC was integrated on a dc-dc magnetic-less boost converter able to operate at a frequency of 1 MHz. The IC performance and footprint are compared to the same circuit realized with discrete Si and SiC vertical devices, showing the potential of GaN power ICs for efficient and compact power converters.

Role of quantum capacitance on the random dopant fluctuation induced threshold voltage variability in junctionless InGaAs FinFETs

This paper reports an investigation of the effects of varying different device parameters on the random-dopant-fluctuation (RDF) induced threshold voltage variability (σVT) in junctionless (JL) InGaAs FinFETs. Such investigation is made by means of a 3D numerical device simulator. Both gate length and fin height scaling are found to increase σVT in InGaAs JL FinFETs, similar to that in Si devices, following “Pelgrom’s law” [1]. On the other hand, although the scaling of either fin width (Wfin) or effective oxide thickness (EOT) of the gate insulator reduces σVT in Si JL devices due to enhanced electrostatic integrity; such scaling is found to deteriorate σVT in InGaAs JL FinFETs. Decrease in the density of state capacitance, also known as quantum capacitance, with Wfin or EOT scaling is found responsible for the deterioration of σVT in InGaAs devices.

Tuning the high-κ oxide (HfO2, ZrO2)/4H-SiC interface properties with a SiO2 interlayer for power device applications

SiC based power devices are promising for the next generation energy-efficient power converters. But its device performance is always largely limited by the tradition thermal SiO2 gate dielectric. The high-κ dielectric gate oxides have been widely used in Si and III-V devices. However, high quality dielectric layer using high-κ oxide for SiC power device is still lacking sufficient theoretical investigation. In this paper, the properties of XO2/4H-SiC (X = Hf or Zr) interfaces with a SiO2 interlayer are systematically studied by density-functional supercell calculations. Reliable interface atomic structures without any gap states have been built according to the electron counting rule. Based on the models, the electronic structure of each interface is obtained by hybrid functional. The interfacial characteristics including the averaged potential and charge transfer analysis are calculated in detail. The calculated band edge line-ups are comparable with the experimental reports. In term of the band alignment, HfO2 and ZrO2 directly bonding to SiC are not suitable dielectric materials for SiC based power device, due to the relatively smaller conduction band offsets (CBO). While introducing the SiO2 interlayer can effectively tune the interface properties, especially the band alignment. With HfO2(ZrO2)/SiO2 stack as the dielectric layer for 4H-SiC, the interface has the large CBO (>1 eV) to efficaciously confine the channel carriers, indicating that the HfO2(ZrO2)/SiO2/4H-SiC stack is the promising strategy for SiC based power device applications.

Incorporation of polyvinyl alcohol into ZrO2 to modulate the hysteresis-type current–voltage characteristics of Au/ZrO2/heavily doped p-type Si devices

This study determines the effect of incorporating polyvinyl alcohol (PVA) into ZrO2 (PVA:ZrO2) on the hysteresis-type current–voltage characteristics of Au/ZrO2/heavily doped p-type Si (p+-Si) devices. In order to determine the correlation between morphology and performance, the Au/ZrO2/p+-Si and Au/PVA:ZrO2/p+-Si devices are fabricated and their current–voltage characteristics are determined. These devices exhibit hysteresis. Incorporating PVA into ZrO2 induces a strong steric effect, which results in the elimination of crystallographic defects in the ZrO2 films and an improvement in the hysteresis characteristics for Au/PVA:ZrO2/p+-Si devices. Incorporating PVA into ZrO2 modulates hysteresis in Au/ZrO2/p+-Si devices.

Busbar Design and Optimization for Voltage Overshoot Mitigation of a Silicon Carbide High-Power Three-Phase T-Type Inverter

The silicon carbide (SiC) devices have faster switching speed than that of the conventional silicon (Si) devices, which however may cause excessive device voltage overshoot. Larger gate resistance can help to restrain the overshoot, it however slows down the switching speed and increases switching losses. There are other methods that can mitigate the voltage overshoot, e.g., using low-inductance busbars, adding snubber circuits, etc. In this article, the busbar design for a 250-kW SiC three-level T-type inverter is investigated. The current commutation loops (CCLs) are first analyzed using a single-phase equivalent circuit. Then the detailed busbar design methods, especially a 3-D busbar design concept, are proposed to select the optimal stacking order for the multilayer laminated busbar and to address constraints posed by the physical terminal arrangements of SiC modules and dc-link capacitors. The stray inductance in each CCL is extracted via a finite element analysis and validated on the actual inverter busbar prototypes using an impedance analyzer. To further minimize the busbar stray inductance, a hybrid busbar structure with printed circuit board based buffer circuit using high-frequency decoupling capacitors is designed and evaluated in this article. Finally, the effectiveness of the designed busbars as well as the buffer circuit are validated using experimental studies.

Memristive and Synaptic Characteristics of Nitride-Based Heterostructures on Si Substrate.

Brain-inspired artificial synaptic devices and neurons have the potential for application in future neuromorphic computing as they consume low energy. In this study, the memristive switching characteristics of a nitride-based device with two amorphous layers (SiN/BN) is investigated. We demonstrate the coexistence of filamentary (abrupt) and interface (homogeneous) switching of Ni/SiN/BN/n++-Si devices. A better gradual conductance modulation is achieved for interface-type switching as compared with filamentary switching for an artificial synaptic device using appropriate voltage pulse stimulations. The improved classification accuracy for the interface switching (85.6%) is confirmed and compared to the accuracy of the filamentary switching mode (75.1%) by a three-layer neural network (784 × 128 × 10). Furthermore, the spike-timing-dependent plasticity characteristics of the synaptic device are also demonstrated. The results indicate the possibility of achieving an artificial synapse with a bilayer SiN/BN structure.

Analysis of Large-Signal Output Capacitance of Transistors Using Sawyer–Tower Circuit

A detailed analysis of the Sawyer–Tower method used in the measurement of large-signal output capacitance ( $\boldsymbol {C}_{{\textrm {o}}}$ ) of power transistors is presented, followed by important design recommendations to obtain accurate results. Key factors affecting the proper implementation of the technique, such as power amplifier characteristics, load slew rate, reference capacitor ( $\boldsymbol {C}_{\text {ref}}$ ), and reverse conduction of the device, are addressed, with accompanying simulation and experimental results for Si, SiC, and GaN devices. A thorough investigation of the selection of $\boldsymbol {C}_{\text {ref}}$ is presented, with a new equation to correctly determine its value for a given voltage swing and output capacitance range of the device under test (DUT). We report that the Sawyer–Tower circuit imposes the DUT to enter steady-state reverse conduction under certain conditions, thus leading to charge–voltage ( QV ) hysteresis patterns unrelated to $\boldsymbol {C}_{{\textrm {o}}}$ . Our analysis reveals that the origin of this phenomenon is related to DUT’s leakage current and it could be minimized by the proper selection of excitation frequency. This article intends to provide an effective guide on designing and using the Sawyer–Tower circuit, and to induce further scientific insight on characterizing $\boldsymbol {C}_{{\textrm {o}}}$ .

(Invited) Doping Considerations for Finfet, Gate-All-Around, and Nanosheet Based Devices

The semiconductor industry has been based on Si device scaling for many decades. The motivation for scaling Si is well known, as the reduced dimensions can lead to increased field-effect transistor (FET) device (logic) performance with lower power consumption, thereby enabling a vast array of consumer electronic products. While other materials such as Ge, III-Vs, and 2D materials have threatened to replace Si in FET device channels, it remains at the core of modern digital logic transistors and circuits.Si has been scaled below 10 nm in multi-gate and silicon-on-insulator (SOI) device technologies, but its thickness cannot be reduced indefinitely and larger surface-to-bulk ratios will impact the behaviour of the Si. In general, surface physics cannot be discounted as thickness approaches 5 nm. It is known that effects must be considered at these scales such as carrier surface scattering, dielectric screening, interface states, as well as decreased doping efficiency, increased dopant trapping, and an increase in Si bandgap. If not properly controlled, or at least understood, these factors may inhibit proper semiconductor operation.Damage-free doping processes are desirable as crystal defects or surface roughness can, not only, negatively impact individual transistor device performance, but can also introduce an uncontrolled variability among devices. A conformal process implies access to all surfaces equally in order to, in this case, uniformly and reliably modify the material. Uniformity is necessary as it reduces local resistance variation which again can lead to poor electrical behaviour. As we transition to Gate-All-Around (GAA) device architectures, where all sides of the semiconductor are accessible in theory, having processes that can actually demonstrate access to the bottom surface are becoming increasingly sought after. When dealing with 3D structures the impact of surface effects becomes crucial in determining the active dopant levels. These surface effects lead to problems for dopant incorporation/activation or as gettering points where dopants pile up. Another problem with the greater exposure to the perimeter of the 3D devices is when the doping process etches the available surface, severely damaging or destroying these devices.In this presentation we will consider doping techniques based on ion implant, solid-source in-diffusion, liquid-source in-diffusion, and gas-source in-diffusion. As Si devices scale, the effect of beamline induced crystal damage compounds as a greater percentage of the device area will consist of damaged crystal. Beamline induced surface damage will become a more prominent issue with increasing surface to volume ratios of Si devices. Sputtering of the Si surface by the ion beam is likely to become a more limiting factor once device pitch becomes scaled limiting the acceptable implantation angles. Limitation of the beamline angles will lead to shadowing of the Si devices, and therefore asymmetrical dopant levels. With the advent of GAA devices, line-of-sight implantation methodologies may be unsuitable for the doping of 3D stacked devices.On the other hand in-diffusion techniques suffer due to a surface barrier that must be overcome in order to enter the Si, while ions can always be implanted beyond the surface into the target. Pioneering solutions may exist in the fields of proximity doping and novel surface passivation techniques. Gas-phase doping has a greater potential than liquid or solid phase processes to dope the increasingly complex 3D geometries of Si devices as liquid coverage can be limited by wetting, and solid sources can be limited when fin and nanowire pitches are scaled.

Cu-Ag Alloy By Using Chemical Displacement Method for Resistive Random-Access Memory

Resistive random-access memory is one of the most promising candidates for the next generation nonvolatile memory due to the simple metal-insulator-metal structure, fast program speed, and compatibility with CMOS technology. It’s switching mechanism is control by metallic ions to form the metal filament between device electrodes, typical CBRAM uses active metal elements as a source of metal ions, such as Copper and Silver. In this study, a bottom electrode of a different proportions Cu-Ag alloy made by chemical displacement technique was compared in terms of resistance switching properties for a silicon dioxide based RRAM device. The result shows the process voltage decrease, stability increase and at least an order of memory window and only a very small percentage of silver is needed as a catalyst to trigger this mechanism.ReRAM devices are the most excellent in the nonvolatile memory, compare with flash memory devices, it has lower fabrication cost. For ECM-type ReRAM, an active metal, such as copper or silver, is used for anode oxidation, and cathode reduction reaction occurs to establish the conduction filament in the switching layer. Cu is used widely in ECM-type ReRAM because the price is cheaper than Ag. However, Cu is difficult to dry-etch, and its residue after the etching process contaminates the Si device. The Cu etching problem hinders the development of Cu-based ReRAM. In this paper, a bottom electrode of a different proportions Cu-Ag alloy made by chemical displacement technique (CDT) was compared in terms of resistance switching properties for a silicon dioxide based RRAM device, and only a very small percentage of silver is needed to trigger the mechanisms, not only significantly reducing set voltage and reset voltage but also be more stable. Figure 1 illustrates the fabrication process of the Al/SiO2/Cu-Ag/Si ReRAM device. After RCA cleaning, the wafer is placed in a solution at different concentrations to deposit 60 sec, 120 sec, 180 sec to displace the metal, and the solution formula is as Table 1, then the wafer is cleaned with DI-Water, after cleaning, the wafer surface water stains are removed with nitrogen gun to form a subelectrode to complete the metal lower electrode and then E-Gun deposits a layer of 30 nm thick silicon as an insulation layer, finally, a 100 nm Al as the top electrode layer was deposited by evaporator with metal mask. The diameter of each sample was 100μm. And the evaporator Cu (Ag)/SiO2/TaN/SiO2/Si was prepared as the control sample. Figure 2 are J–E characteristic curves of Cu Ag alloy-CDT ReRAM devices, the J-E shows that larger operating voltage is required to operate than a CDT-Cu that is not added the silver, since the reset voltage of pure metal is larger than Cu-Ag alloy. The difference between Cu-Ag alloy components and metal components are that decreasing the forming voltage, but as the Ag of the alloy increases, there is no significant proportional change in the forming voltage.As shown in Figure 3 That in alloy components, silver as the main catalyst to accelerate the formation of Cu filament, chemical displacement method to prepare the alloy electrode components of the assembly operating the electric field is relatively small and stable compare to the Cu electrode assembly, set voltage will also be reduced, because the metal atoms based on the dissociation energy and metal ion react, and Ag dissociation energy is smaller than Cu, represents the Ag atom that is more active than the Cu atom.In the alloy devices, the Ag atom will capture the Cu atom’s electrons, making the Cu ions more easily dissociation and forming the filament, but need a very small percentage as a catalyst can accelerate the Cu ion dissociates to form the filament, and because of the influence of Ag, resulting in the formation of Cu filament, which needs a lower electric field to fuse. As shown in figure 4, the data retention of pure metal components and Cu-Ag alloy components, respectively as CDT-Cu, although the Ag forming filament is thinner.In this paper, silicon is replaced with Cu-Ag alloy by chemical displacement method without electroless plating, with the advantages of random blend alloy ratio, can also be controlled the surface roughness of the film by different displacement time. On the other hand, Ag atoms obtain the electrons of the Cu atoms, making it easier for Cu ions to dissote and forming a filament, so adding Ag not only reduces the operating electric field, but also makes the electric field more concentrated, and maintain the data retention at the same order magnitude. Figure 1

Graphene/Au/SiC Optical Waveguide-Based Surface Plasmon Resonance Sensor for Chemical and Biomedical Sensing in Aqueous Medium

In chemical and biomedical sensing, identification and quantification of analytes in aqueous medium such as water, blood or other carriers are very important. It requires the core sensors to have the properties of low cost, high sensitivity, on-chip integration capability, etc. Various sensing methods have been developed such as prism coupler and grating coupler, etc. and among them, waveguide-based surface plasmon resonance (SPR) sensors, with sensitivity of the optical waveguide significantly improved by SPR, have been identified as a powerful tool for detection and quantitative characterization of chemical and biological species or biomolecular reactions in aqueous medium. For sensing in aqueous medium, the optical waveguide sensors are desirable to operate in the visible light wavelength to overcome the large absorption coefficient of water in the near infrared range. This high absorption coefficient causes optical energy in the near infrared incident light be absorbed by water rather than by the sensing medium. Conventional silicon (Si) is not the choice of material for such sensors due to the strong absorption below the wavelength of 1.1 μm due to its narrow bandgap (Eg=1.12 eV, 1.1 µm wavelength).As a wide bandgap semiconductor, silicon carbide (SiC) is more desirable for such sensors with advantages of: (1) bandgap energy of 3.2 eV in 4H and 6H polytypes and 2.2 eV in 3C polytype with transparent wavelength in visible and near-infrared range, (2) excellent material properties especially the chemical inertness and biocompatibility, and (3) device fabrication compatibility with standard Si device fabrication for manufacturing and on-chip integration. Therefore, SiC is a desirable material candidate for SPR sensors for chemical and biomedical sensing in aqueous medium, and approaches to enhance its sensitivity have been explored. 2-D materials such as graphene, TMDCs (MoS2, WS2, MoSe2, WSe2), etc. and their applications in sensing technology has aroused wide attention because of their distinctive electrical and optical properties. SPR sensors with 2-D and Si to enhance the sensitivity have been studied by publications. In this paper, we investigated graphene/Au/SiC waveguide-based SPR sensors (Fig. 1) for aqueous medium sensing. The resonance frequency shift with different numbers of graphene layer were studied (Fig. 2). Comparison of resonance wavelength shift from conventional and proposed sensor were performed (Fig. 3). At the incident light of 633 nm, the confinement factor above 0.9 can be achieved at the refractive index of n=1.3~1.5. With the change of refractive index, the shift of resonant wavelength showed linear characteristics, and a sensitivity of 2580 nm/RIU (refractive index unit) was obtained in a refractive index range of n=1.34~1.36 (Fig. 4). Figure 1

Thermoelectric properties of holey silicon at elevated temperatures

Compatibility to the semiconductor industry makes silicon thin-film devices attractive for thermoelectric applications. Silicon has a competitive thermoelectric power factor but a large thermal conductivity, which results in an overall small thermoelectric figure of merit, ZT. By patterning arrays of nano-sized holes with spacing less than the average phonon mean free path into the Si thin films, their thermal conductivity can be greatly suppressed, whereas their electronic properties are less affected. We fabricated and measured the electronic and thermal transport properties of such holey Si devices from 300 K to 650 K. Heat diffusion imaging, a hybrid approach that combines thermoreflectance imaging and the heat spreader method was used for the in-plane thermal conductivity measurement and gives a value of 6.00 ± 1.83 W/mK at room temperature. The power factor times temperature is about 0.52 ± 0.04 W/mK at 300 K and 1.10 ± 0.09 W/mK at 650 K. Therefore, ZT of the holey Si device is approximately 0.09 at room temperature and is at least 0.29 at 650 K. Further improvement is possible by optimizing the feature sizes and using surface doping.

Electron transport analysis of 4H-SiC with full-band Monte Carlo simulation including real-space Coulomb interactions

4H-SiC has been widely used in many applications. All of these benefit from its extremely high critical electric field with good electron mobility. 4H-SiC possesses a critical field ten times higher than that of Si, which allows high-voltage blocking layers composed of 4H-SiC to be approximately a tenth the thickness of a comparable Si device, thus reducing the device on-resistance and power losses, while maintaining the same high blocking capability. Unfortunately, commercial Technology for Computer-Aided Design tools like Sentaurus and Silvaco Atlas are based on effective mass approximation, while most 4H-SiC devices are not operated under a low electric field so the parabolic-like band approximation does not hold anymore. Hence, to get more accurate and reliable simulation results, full-band analysis is needed. The first step in the development of a full-band device simulator is the calculation of the band structure. In this work, the empirical pseudopotential method is adopted. The next task in the sequence is the calculation of the scattering rates. Acoustic, non-polar optical phonon, polar optical phonon, and Coulomb scattering are considered. Coulomb scattering is treated in real space using the particle–particle–particle–mesh approach. The third task is coupling the bulk full-band solver with a 3D Poisson equation solver to generate a full-band device simulator. For proof-of-concept of the methodology adopted here and for simplicity, a 3D resistor is simulated. From the resistor simulations, the low-field electron mobility dependence upon Coulomb scattering in 4H-SiC devices is extracted. The simulated low-field mobility results are in excellent agreement with available experimental data.

Voltage Balancing Control of Series-Connected SiC MOSFETs by Using Energy Recovery Snubber Circuits

Power semiconductor switches are usually connected in series to achieve higher blocking voltage. However, the series-operation of semiconductor devices is not easy due to unequal voltage sharing. In comparison with silicon (Si) devices, series-connecting silicon carbide (SiC) devices are even more challenging due to their ultrafast switching speed. In this article, a novel snubber circuit topology with energy recovery capability is proposed to control the voltage sharing of series-connected SiC mosfet s. The snubber circuits operate with a self-balancing technique; thus, the required control and sensing circuits are simple. The proposed method maintains the snubber capacitor voltage nearly constant, so the snubber capacitors are not fully discharged during the devices on -state. Besides, excess snubber energy can be transferred back to the dc bus, so the induced snubber loss is minimal. Experimental results show the effectiveness of the proposed snubber circuit topology in a half-bridge inverter with four SiC mosfet s connected in series.

Fabrications of Hetero-Junction Schottky Diodes by Electrodeposition of Nano-Structured CuInSe2 Materials Using Different Upper Electrodes

In this study, CuInSe2 (CIS) films (CIS-TFs) and nanorods (CIS-NRs) were successfully deposited on Mo/glass and p+-silicon (p+-Si) using an electrodeposition method. Anodic aluminum oxide (AAO) was used as the template when the CIS-NRs were deposited. Pt, indium tin oxide (ITO), and Ag were deposited as the upper electrodes using a sputtering method to form the hetero-junction devices of Pt/CIS-NRs/p+-Si, ITO/CIS-NRs/p+-Si, ITO/CIS-TF/Mo/glass, and Ag/CIS-NRs/p+-Si, respectively. When p+-Si was used as the substrate, Al was deposited on p+-Si to form negative electrodes for the devices of Pt/CIS-NRs/p+-Si, ITO/CIS-NRs/p+-Si, and Ag/CIS-NRs/p+-Si. The current–voltage properties of all the hetero-junction devices were measured and we found that the hetero-junction of ITO/CIS-NRs/p+-Si, ITO/CIS-TF/Mo/glass, and Ag/CIS-NRs/p+-Si devices revealed the properties of Schottky diodes but the hetero-junction device of Pt/CIS-NRs/p+-Si device did not. The reason for the cause of the differences between these hetero-junction devices was investigated for this study.

Inverted Si:PbS Colloidal Quantum Dot Heterojunction-Based Infrared Photodetector.

Silicon and PbS colloidal quantum dot heterojunction photodetectors combine the advantages of the Si device and PbS CQDs, presenting a promising strategy for infrared light detecting. However, the construction of a high-quality CQDs:Si heterojunction remains a challenge. In this work, we introduce an inverted structure photodetector based on n-type Si and p-type PbS CQDs. Compared with the existing normal structure photodetector with p-type Si and n-type PbS CQDs, it has a lower energy band offset that provides more efficient charge extraction for the device. With the help of Si wafer surface passivation and the Si doping density optimization, the device delivers a high detectivity of 1.47 × 1011 Jones at 1540 nm without working bias, achieving the best performance in Si/PbS photodetectors in this region now. This work provides a new strategy to fabricate low-cost high-performance PbS CQDs photodetectors compatible with silicon arrays.

A High-Efficiency Three-Level ANPC Inverter Based on Hybrid SiC and Si Devices

Silicon carbide (SiC) devices have excellent performance, such as higher switching frequency and lower switching loss compared with traditional silicon (Si) devices. The application of SiC devices in inverters can achieve higher efficiency and power density. In recent years, the production process of SiC devices has become more mature, but the cost is still several times that of traditional Si devices. In order to balance cost and efficiency, replacing only some of the Si devices with SiC devices in a topology is a better choice. This paper proposed a high-efficiency hybrid active neutral point clamped (ANPC) three-level inverter which has only two SiC devices and the other devices are Si devices. A specific modulation strategy was applied to concentrate switching losses on the SiC devices and reduce the on-state loss through parallel operation during freewheeling intervals. Theoretical efficiency curves and experimental verification of the proposed hybrid scheme with Si-only and SiC-only schemes were carried out.