Tuning the high-κ oxide (HfO2, ZrO2)/4H-SiC interface properties with a SiO2 interlayer for power device applications

Abstract

SiC based power devices are promising for the next generation energy-efficient power converters. But its device performance is always largely limited by the tradition thermal SiO2 gate dielectric. The high-κ dielectric gate oxides have been widely used in Si and III-V devices. However, high quality dielectric layer using high-κ oxide for SiC power device is still lacking sufficient theoretical investigation. In this paper, the properties of XO2/4H-SiC (X = Hf or Zr) interfaces with a SiO2 interlayer are systematically studied by density-functional supercell calculations. Reliable interface atomic structures without any gap states have been built according to the electron counting rule. Based on the models, the electronic structure of each interface is obtained by hybrid functional. The interfacial characteristics including the averaged potential and charge transfer analysis are calculated in detail. The calculated band edge line-ups are comparable with the experimental reports. In term of the band alignment, HfO2 and ZrO2 directly bonding to SiC are not suitable dielectric materials for SiC based power device, due to the relatively smaller conduction band offsets (CBO). While introducing the SiO2 interlayer can effectively tune the interface properties, especially the band alignment. With HfO2(ZrO2)/SiO2 stack as the dielectric layer for 4H-SiC, the interface has the large CBO (>1 eV) to efficaciously confine the channel carriers, indicating that the HfO2(ZrO2)/SiO2/4H-SiC stack is the promising strategy for SiC based power device applications.