Si Devices Research Articles

A Comparative Analysis of Efficiency and Losses in a 5 kW Hybrid and Full-SiC Converter, for PV Applications in Austria

Wide Bandgap (WBG) devices like SiC-MOSFETs have become quite popular in recent times due to their superior switching characteristics, high current carrying capability and temperature stability. They are being adopted for many different applications and for a wide range of power levels. For the case of PV applications, manufacturers are considering moving to SiC-based topologies due to higher converter efficiencies and improved power density. However, the present industry largely uses hybrid approaches (IGBT + SiC-diode) to optimize system cost. The aim of this paper is to present a fair comparison of an industry-grade hybrid converter with another similar counterpart where only the Si device has been replaced with the SiC device. The effects of such a direct replacement on the efficiency and losses of the converter are studied under various power ratings. Both converters consist of two stages—a boost converter and a three-phase three-level DC to AC converter. Simulation and experimental results comprehensively indicate a higher efficiency (improvements of up to 8 percent points) for the full-SiC converter, and this is more prominent at low input voltages, where the boost converter is active. However, the gains in efficiency are moderate for high input voltages (1 percent point at nominal voltage), where the boost converter is bypassed, and the losses are almost entirely attributed to the inverter. When set in the backdrop of the Austrian inverter market, the use of SiC devices in PV inverters has the potential for an estimated savings of 37.5 GWh/year in terms of loss reduction.

Enhancing and mapping thermal boundary conductance across bonded Si-SiC interface

SiC is a promising substrate for Si-on-insulator (SOI) wafers for efficient thermal management owing to its high thermal conductivity and large bandgap. However, fabricating a Si device layer on a SiC substrate with a high and uniform thermal-boundary conductance (TBC) at the wafer scale is challenging. In this study, a 4-inch Si-on-SiC wafer was fabricated using a room-temperature surface-activated bonding method, and the TBC was measured using the time-domain thermoreflectance (TDTR) method. The obtained TBC was 109 MW/m2K in the as-bonded sample, improving to 293 MW/m2K after annealing at 750 °C, representing a 78 % increase compared to previously reported values for a Si–SiC interface formed by bonding methods. Such enhancement is attributed to the absence of an oxide layer at the interface. Furthermore, we assessed the actual spatial distribution of the TBC in the SOI system by combining the TDTR mapping with a mathematical model to remove the influence of random errors in the experiment. The spatial distributions before and after annealing were 7 % and 17 %, respectively. Such variation highlights the need to consider the TBC distribution when designing thermal management systems.

Modelling and Evalaution of the Bidirectional Surge Current Robustness of Si(-IGBT and -Diode), SiC(-MOSFETs and -JFET) and GaN(-HEMTs) Devices

This paper will evaluate the surge current robustness of different devices in relation to the active short circuit (ASC). For the purposes of this study, a Si IGBT and its diode, two SiC MOSFETs with different voltage ratings, a SiC JFET, and three GaN HEMTs will be compared. For the GaN devices, a eMode, a dMode, and a cascode device are employed. With the exception of the Si diode, all devices exhibited a current saturation effect. This saturation will result in significant losses and, ultimately, a thermal defect. For all devices, a safe operating area (SOA) criterion is established. For the SiC and GaN devices, the saturation voltage can be employed to define the safe operating area (SOA) criterion. In this context, two on-state resistance models will be defined for these devices. One is solely temperature-dependent, while the other also considers current saturation. Consequently, the saturation voltage and the on-resistance model represent a straightforward methodology for evaluating the ASC robustness of the devices. For all devices, a recommendation for a loss model and SOA criterion will be provided. Finally, the surge current robustness of all devices is compared. The Si, SiC and GaN devices exhibit comparable high surge current robustness in the application, with the exception of the GaN eMode, which is susceptible to strong current saturation.

Aligned Semiconducting Carbon Nanotubes for Commercial Logic and RF Electronics

Carbon nanotubes are exceptional semiconductors that offer larger current densities and faster switching than conventional Si and GaAs devices, making nanotubes promising for meeting the performance and energy efficiency needs of next-generation electronics. However, the successful commercialization of carbon nanotubes necessitates the control over semiconducting purity, alignment, packing density, and scalability. The simultaneous control of these characteristics has been a major challenge preventing the integration of nanotubes in industrial electronics and the full exploitation of their electronic properties. This talk will present an overview of recent technological developments and methods that progress towards these goals.In these methods, semiconducting (purity of >99.99%) carbon nanotubes are deposited on target substrates via scalable alignment methods at room temperatures. These individual methods separately enable the deposition of quasi-aligned (±28°) nanotube arrays (~50 nanotubes µm-1) demonstrated across 100 mm substrates, highly-aligned (±6°) nanotube arrays (~100 nanotubes µm-1) demonstrated across 100 mm substrates, and the selective-area deposition of highly-aligned nanotube (±7°) arrays (~up to 250 nanotubes µm-1). The nanotube arrays with high packing density (~250 nanotubes μm-1) yield exceptional current densities of 2 mA μm-1 and transconductances of 1 mS μm-1 at VD of -0.6V. Importantly, due to the low-temperature nature of the deposition processes, these techniques offer a direct path towards the alignment of carbon nanotubes directly on Si and other materials, such as GaN or plastics, to enable high-performance 3D integrated circuits.

(Invited) Biofabricated Carbon Nanotube Electronics: Toward Energy-Efficient Switches in Multi-Dimensional Integration

High-performance Si devices are approaching their physical boundaries during the continuous miniaturization following Moore's Law. New semiconductor materials are in urgent necessity, among which, carbon nanotubes（CNTs）are suggested by the International Technology Roadmap for Semiconductors（ITRS）as potential candidate to continue Moore's Law due to its quasi-one-dimensional structure and excellent electrical properties.To unleash the advantages of CNTs in the post-Moore era, optimizing materials morphology, interfaces composition, and integrated structure proves to be pivotal, which constitutes the basic idea of our research. Regarding material morphology, we have fabricated evenly spaced parallel CNT materials with a spacing down to 10nm, by employing the DNA-directed high-precision assembly method. At CNT interface, we have realized fast on/off switching high-performance switches by engineering the interfacial compositions. Individual CNT displays 1G0 conductance with subthreshold swing superior to conventional Si transistors. Furthermore, we built the preliminary foundation to integrate CNT transistors into multi-dimensional circuits. Based on the control of material, interface, and integration structure, our work elucidates the potential of constructing energy-efficient computing circuit using carbon nanotube electronics.

Cross-architecture tuning of silicon and SiGe-based quantum devices using machine learning

The potential of Si and SiGe-based devices for the scaling of quantum circuits is tainted by device variability. Each device needs to be tuned to operation conditions and each device realisation requires a different tuning protocol. We demonstrate that it is possible to automate the tuning of a 4-gate Si FinFET, a 5-gate GeSi nanowire and a 7-gate Ge/SiGe heterostructure double quantum dot device from scratch with the same algorithm. We achieve tuning times of 30, 10, and 92 min, respectively. The algorithm also provides insight into the parameter space landscape for each of these devices, allowing for the characterization of the regions where double quantum dot regimes are found. These results show that overarching solutions for the tuning of quantum devices are enabled by machine learning.

Critical factors for enhancing electrical performance in LaGdO3 capacitor

This study investigates the characteristics of metal/LaGdO3/Si capacitors using LaGdO3 as the dielectric material. LaGdO3 thin films were deposited using radio-frequency magnetron sputtering, and the effects of different process parameters, such as annealing temperature, electrode materials, and oxygen ratio, on the capacitance characteristics were investigated. Results showed that the presence of oxygen vacancies affects the dielectric constant, flat-band voltage, and breakdown field of LaGdO3 films. The optimal annealing temperature for the LaGdO3/Si stack was identified to be 600 °C, resulting in a dielectric constant of 13.9 and a flat-band voltage shift of 0.1 V. Introducing 10 % O2 during deposition effectively repaired oxygen vacancies in the film, while excessively high oxygen proportions resulted in a lower dielectric constant and a higher flat-band voltage shift. Moreover, the electrode material was found to affect the capacitance characteristics. The dielectric constants for Al/LaGdO3/Si, Ti/LaGdO3/Si, and Pt/Ti/LaGdO3/Si capacitors were 10.0, 16.3, and 17.3, respectively. The flat-band voltage shifts were −0.7, −0.42, and −0.03 V, with hysteresis voltages of 345, 117, and 32 mV, respectively. The Pt/Ti/LaGdO3/Si device exhibited the lowest oxide defect density, indicating superior interface quality and potentially enhanced device performance. In addition, the band diagrams for metal/LaGdO3/Si were constructed. This study demonstrates that oxygen vacancies and electrode materials are crucial factors influencing the capacitance characteristics of LaGdO3 films. The electrical properties of LaGdO3 films can be effectively improved by controlling process parameters, enhancing their potential for applications in capacitors and other electronic devices.

Nonvolatile bipolar resistive switching characteristics of aluminum oxide grown by thermal oxidation processes

This study proposes a bipolar resistive random-access memory (RRAM), which is fabricated using an aluminum oxide (AlO x ) resistive switching (RS) layer. The RRAM shows a large memory window of 106 at a low read voltage of 0.5 V. In addition, high switching speed, long retention time, and superior read-disturb immunity are observed. AlO x layers are prepared by a thermal oxidation growth process. Aluminum metal films deposited on n+-Si wafers are oxidized at O2/(O2 + N2) flow rate ratios of 50%–100%. Al/AlO x /n+-Si device shows no RS behavior when the AlO x is grown in a pure O2 environment. As the O2/(O2 + N2) flow rate ratio decreases to 50%, Al/AlO x :N/n+-Si device reveals stable bipolar RS characteristics. A filamentary mode based on oxygen interstitial and Al vacancy is proposed to explain the difference in electrical characteristics of AlO x devices prepared at different O2 flow rates.

Compact light couplers for lateral III-V membrane devices grown on SOI platforms.

Compact light couplers between III-V devices and Si waveguides are crucial for advancing the scalability of Si photonics. Here, we present a compact light coupling strategy for lateral III-V membrane lasers and PDs directly grown on SOI platforms. Benefiting from the coplanar configuration of epitaxial III-V membranes and Si device layer, we designed novel, to our knowledge, butt couplers to achieve both small footprint and high efficiency coupling. We employed sub-wavelength grating structures to gradually bridge the effective refractive index between the III-V membranes and Si waveguide and obtained a coupling loss of less than 0.5 dB across the entire telecom band in a length of less than 10 μm. Our work here offers a fresh perspective for future densely integrated Si photonics.

Input-parallel output-series Si-SiC hybrid inverter with fractional harmonic elimination

This paper proposes an input-parallel output-series (IPOS) Si-SiC hybrid inverter with dual-frequency harmonic elimination modulation strategy. The proposed topology composed of two power conversion cells and a three-phase five-column medium-frequency step-down transformer, the low-frequency power conversion cell (LFPC-C, 1 kHz) leverages strong current-carrying capacity of silicon-based devices for dealing with the system main power, and the high-frequency power conversion cell (HFPC-C, 30 kHz) based on wide-bandgap semiconductor SiC devices is used to addressing the fractional harmonics compensation power. This topology combines the strong current carrying capability of Si devices with the low switching loss of SiC devices at high frequency and achieves high quality power conversion at low cost and low loss. Compared to existing “IPOP” Si-SiC hybrid inverters, this topology adopts a coupling step-down transformer on the output side of both LFPC-C and HFPC-C, which can effectively reduce current stress of HFPC-C SiC devices. Additionally, a dual-frequency harmonic elimination modulation strategy based on the topology is proposed to solve the fractional harmonics caused by the LFPC-C. The paper establishes a mathematical model according to the harmonic distribution characteristics of the LFPC-C and HFPC-C, and designs the system control schedules. Building upon the derivation of the voltage ripple model and the design of hardware parameters, Si IGBT and SiC MOSFET were selected for constructing a 7.5 kW prototype for testing, and the experimental results validate the feasibility of this topology and the accuracy of theoretical analysis.

Determination of the effective critical breakdown field for Si, wide, and extreme bandgap semiconductor superjunction devices

Designing high voltage superjunction (SJ) power devices with wide bandgap and extreme bandgap semiconductors, when compared to silicon, can enhance the trade-off between RON,sp and BV significantly, due to their >10× higher avalanche breakdown electric field. Nevertheless, because of the difference in the breakdown field profile and ionization path length, the effective breakdown field for these semiconductor SJ devices has not been determined theoretically. Consequently, we estimate and compare the effective critical breakdown electric field for SJ device structures in Si, 4H–SiC, 2H–GaN, β-Ga2O3, diamond, and AlN using Technology Computer Aided Design TCAD simulation. We also establish its dependence on the SJ devices’ structural parameters, such as the pillar thickness. Furthermore, we also quantitatively compare the on-state performance of these SJ devices, including their thermal capabilities, using a paramount figure-of-merit to underscore the potential improvement possible.

A Hybrid Cascaded Multilevel Converter Based on Si and SiC Devices and Its Regulation Optimization Strategy

A Hybrid Cascaded Multilevel Converter Based on Si and SiC Devices and Its Regulation Optimization Strategy

Nonvolatile memory operations using intersubband transitions in GaN/AlN resonant tunneling diodes grown on Si(111) substrates

Nonvolatile memory using intersubband transitions and quantum-well electron accumulation in GaN/AlN resonant tunneling diodes (RTDs) is a promising candidate for high-speed nonvolatile memory operating on a picosecond timescale. This memory has been fabricated on sapphire(0001) substrates to date because of the high affinity between the nitride materials and the substrate. However, the fabrication of this memory on Si(111) substrates is attractive to realize hybrid integration with Si devices and nonvolatile memory and three-dimensional integration such as chip-on-wafer and wafer-on-wafer. In this study, GaN/AlN RTDs are fabricated on a Si(111) substrate using metal-organic vapor phase epitaxy. The large strain caused by the differences in the thermal expansion coefficients and lattice constants between the Si(111) substrate and nitride materials are suppressed by a growth technique based on the insertion of low-temperature-grown AlGaN and thin AlN layers. The GaN/AlN RTDs fabricated on Si(111) substrates show clear GaN/AlN heterointerfaces and a high ON/OFF ratio of >220, which are equivalent to those for devices fabricated on sapphire(0001) substrates. However, the nonvolatile memory characteristics fluctuate by repeated write/erase memory operations. Evaluation of the ON/OFF switching time and endurance characteristics indicates that the instability of the nonvolatile memory characteristics is caused by electron leakage through deep levels in the quantum-well structure. Possible methods for suppressing this are discussed with an aim of realizing high-speed and high-endurance nonvolatile memory.

1072 SIJ Fusion Device Testing

INTRODUCTION: Screw use for SIJ fixation began in the 1980s with the FDA first classifying SIJ fusion devices in 2002. For 40 years, no standardized test method existed. Various methodologies (for bone screw, intramedullary nail, or spinal fusion implants) were modified to accommodate the design and function of sacroiliac devices including ASTM F543’s torsion, pullout, and insertion tests, ASTM F1264’s three- or four-point bending tests, and ASTM F2193’s cantilever bending tests. For many years, SIJ fusion screw indications were limited to fixation of pelvic bones for sacroiliac joint disruptions and degenerative sacroiliitis. While the FDA typically accepted performance testing according to combinations of the aforementioned tests, the specific test expectations have been relatively undefined with inconsistent testing batteries from submission to submission. METHODS: Collaboration among testing experts, manufacturers, and FDA regulators within ASTM’s Spinal Devices sub-committee resulted in the development and publication of ASTM F3574 (Standard Test Methods for Sacroiliac Joint Fusion Devices) based on physiologic loading conditions in the joint as documented in published studies. These tests included: For SI Screws: • Static/dynamic cantilever bending •Static torsion •Driving torque •Pullout For SI Posterior Spacers: •Static/dynamic shear •Static/dynamic torsion. RESULTS: The medical device industry now has access to standardized test methods for SI devices while the FDA or other regulators now have device specific test methods to recommend for pre-clinical testing. CONCLUSIONS: Many new standards drag through years of development and refinement within sub-committees, but ASTM F3574 developed quickly due to efforts of the Spinal sub-committee task group to meet the needs for SI fusion devices.

Barium titanate write-once read-many times resistive memory with an ultra-high on/off current ratio of 108

Write-once read-many times (WORM) resistive memories fabricated using perovskite barium titanate (BaTiO3, BTO) resistive switching (RS) layer are demonstrated in this study. The BTO RS layers with thicknesses of 3.2–8.5 nm are fabricated by radio frequency sputtering at room temperature. Annealing processes at 400–600 °C are used to modify the oxygen vacancy content in the BTO layer and thereby control the OFF-state current of an Al/BTO/n+-Si WORM device. The ION/IOFF ratio increases with increasing annealing temperature until 500 °C. A negative effect is observed when the temperature further rises to 600 °C. The optimal Al/BTO/n+-Si device shows an ultra-high ION/IOFF ratio of 108 and a low coefficient of variation of 6% for set voltages. The writing speed is 80 ns and the power consumption is 400 pJ. In addition, retention and stress tests are performed to confirm high data storage reliability of the device. Mechanisms for voltage-polarity independent writing process and the related energy band diagrams are explored.

Impact of HfO2 Dielectric Layer Placement in Hf0.5Zr0.5O2‐Based Ferroelectric Tunnel Junctions for Neuromorphic Applications

AbstractThe use of Hf0.5Zr0.5O2 (HZO) films within hafnia‐based ferroelectric tunnel junctions (FTJ) presents a promising avenue for next‐generation non‐volatile memory devices. HZO exhibits excellent ferroelectric properties, ultra‐thinness, low power consumption, nondestructive readout, and compatibility with silicon devices. In this study, Mo/HZO/n+ Si devices are investigated, incorporating a 1 nm HfO2 dielectric layer at the top and bottom of the HZO ferroelectric layer. Comparing the FTJ device configurations, it is observed that the metal‐ferroelectric‐dielectric‐semiconductor (MFIS) outperforms the metal‐dielectric‐ferroelectric‐semiconductor (MIFS) in terms of ferroelectricity, displaying a high 2Pr value of ≈69 µC cm−2. Additionally, MFIS exhibits lower leakage current, higher tunneling electro‐resistance ratio, and a thin dead layer during short pulse switching, as confirmed through DC double sweeping of I−V characteristics. The modified half‐bias scheme demonstrates a maximum array size of 191 for MFIS, showcasing its superior performance over MIFS. Synaptic characteristics, including potentiation, depression, paired‐pulse facilitation, spike‐rate‐dependent plasticity, and excitatory postsynaptic current, are measured using MFIS, highlighting its outstanding ferroelectric properties. As a physical reservoir, the FTJ device implements 16 states of 4 bits in reservoir computing. Finally, pattern recognition using a deep learning neural network achieves high accuracy with using the Modified National Institute of Standards and Technology dataset.

Thickness Effect of Copper Clips on Power Module Packaging Design

The superior switching performance of SiC MOSFETs compared to Si devices is limited by packaging-related issues. High electromagnetic parasitics which lead to high voltage overshoots, and higher power losses are the main challenges of high frequency operation. Hence, packaging design modification and optimisation are necessary to accommodate faster switching. Copper clips replacing the bonding wires show promising results in reducing stray inductances, while enhancing the current conduction and heat dissipation since the clip are in contact with a larger area of the semiconductor chip. Silver sintering instead of soldering further improves the electrothermal behaviour. This paper investigates numerically various thicknesses of the copper clips and their effect on double-sided silver sintering, half-bridge 1200V/400A SiC MOSFET power module. Moreover, the silver layer thickness is varied to reduce th maximum stresses on the chip - silver interface.

Surface roughness analysis of Cu seed layer deposited on α-Ti diffusion barrier layer: A molecular dynamics simulation study

Copper (Cu) interconnections have been widely used in advanced electronic packaging due to their outstanding thermal and electric properties. Preparing a smooth and uniform Cu seed thin layer is one of the critical processes to obtain high-reliability Cu interconnections. The barrier layer between Cu and silicon (Si) devices is necessary to prevent the inter-diffusion between Cu and Si. However, little work has been done on the surface roughness analysis of the Cu seed layer deposited on the diffusion barrier layer. In this paper, the influences of deposition thickness, incident energy, barrier layer temperature, and surface morphology on the surface roughness of the Cu seed layer deposited on α-titanium (α-Ti) barrier layer were studied in detail by the molecular dynamics (MD). The simulation results indicated that appropriate parameters have a beneficial effect on reducing the surface roughness, and the surface morphology of the Cu seed layer strongly connects with that of the barrier layer. These results provided a foundation for optimizing the quality of the Cu seed layer.

A partial soft-switching SiC-based ANPC single-phase inverter with loss model-based dead time optimization for grid-tied PV systems

Single-phase string inverter has been widely applied to grid-tied photovoltaic (PV) rooftop applications for its renewable energy. However, the inherent attribute of intermittency in solar energy may induce instability and unqualified power. To meet the grid-interconnection standards, high demands of efficiency and harmonic distortion need to be imposed on DC/AC inverters. Conventional soft-switching inverters used to sacrificing auxiliary resonant circuits to exchange for soft switching. This requires additional costs as well as sufficient dead time to discharge junction capacitances of all switches, which exacerbates total harmonics distortion (THD) induced by dead-time effect. To improve, this paper proposes a partial soft-switching silicon carbide (SiC) -based active neutral-point-clamped (ANPC) inverter, which possesses high efficiency, eligible dead time, and no auxiliaries. 650-V SiC MOSFET is adopted for its smaller output capacitance compared with Si device. Hybrid PWM modulation is utilized to achieve partial soft switching. Whereas, the soft switching realization range and power losses highly depend on the dead time. To achieve less power loss and improved dead time effect, this paper proposes a loss model-based dead time algorithm through a Power Loss VS. Dead Time mathematical loss model. Moreover, the mechanism of the dead time affected by soft switching is explored. The transition modes, dead time configurable boundaries, and design procedure are also analyzed in detail. A 1-kW prototype is demonstrated with the input of 800 V and the rated output of 220 V/ 4.5 A. Its efficiency could reach 99.6% with THD=0.95% at full power level.

Enhancement of NiO/Si solar cell by adding porous silicon and a silicon dioxide SiO2 carrier selective layer

In this work, we fabricated a novel heterojunction, Silicon-based solar cell. We used nickel oxide NiO thin films on porous silicon PS separated by a thin silicon dioxide SiO2 carrier-selective layer p-NiO/(SiO2) PS/(n+) Si (Silicon). For comparison, we also manufactured a p-NiO/(n+) Si device. The Atomic Force microscopy AFM and scanning electron microscopy SEM images highlighted the nanoporous pyramidal like structures for p-NiO/(SiO2) PS/(n+) Si devices that decreased the optical reflectivity to 2 %. From the electrochemical study, low resistance and high minority carrier lifetime (1.44 ms) were estimated for p-NiO/(SiO2) PS/n+-Si. The results are promising and agree with a high power conversion efficiency of 19.52 % for p-NiO/(SiO2) PS/n+-Si versus 3.8 % for p-NiO/Si.