Shorted Gate Research Articles

Design of high efficient low power static logic circuit using SG FinFET

ABSTRACT The increasing demand of integration density improvement and battery-powered device efficiency reduced complementary metal-oxide semiconductor (CMOS) technology node. In the technology of CMOS, the components are mainly affected with leakage power, dynamic switching power, short circuit power, gate oxide tunneling leakage current, sub threshold leakage current, and so on. To reduce the above limitations, design of high efficient low power static logic circuit using shorted-gate (SG) fin field-effect transistor (FinFET) based INput DEPendent (INDEP) in 22 nm CMOS technology (SLC-SG-FinFET-INDEP-22 nm CMOS) approach is proposed in this manuscript. The better selection of inputs to proposed INDEP FinFETs model is used for reducing leakage power. The efficiency of the proposed SLC-SG-FinFET-INDEP-22 nm CMOS technique is analysed using delay, power, power delay product, and stability analysis using noise margin. Thus, the proposed SLC-SG-FinFET-INDEP-22 nm CMOS has attained 21.31%, 41.47% and 12.7% lower delay, 20.87%, 34.5% and 22.41% lower power and 4.5%, 25.7% and 32.11% higher speed than existing methods static logic circuit input-controlled leakage restrainer transistor in 22 nm CMOS (SLC-ICLRT-22 nm CMOS), static logic circuit using self-control leakage-suppression block in 22 nm CMOS technology (SLC-SCLSB-22 nm CMOS), and static logic circuit using computational digital low dropout in 22 nm CMOS technology (SLC-CDLDO-22 nm CMOS) methods, respectively.

Robust Logic Circuits Design Using SOI Shorted-Gate FinFETs

The scaling of planar Metal Oxide Semiconductor Field Effect Transistor (MOSFET) technology has reached to its extremity. Double Gate (DG) device was introduced to derive the benefits of scaling gate lengths. Fin-shaped Field Effect Transistors (FinFETs) proved to be the best architecture to realize a double gate structure. In this paper, a static leakage control technique is proposed and a ring-oscillator of five inverters based on shorted gate (SG) FinFETs is simulated using the technique. The basic logic gates like Inverter, 2-input NAND gate, and 2-input NOR gate are simulated using the proposed technique. Leakage power and Power Delay Product (PDP) optimization of 93.46% and 97.78% has been found in 2-input SG FinFET-based proposed NAND gate compared to that of 2-input SG FinFET-based conventional NAND gate.Also, SG FinFET-based proposed 2-input NOR gate shows 98.03% and 98% optimization of leakage power and PDP,respectively compared to the SG FinFET-based conventional 2-input NOR gate. The proposed SG FinFET-based ring-oscillator shows a leakage power and PDP optimization of 62.12% and 35.56%, respectively in comparison to theconventional SG FinFET-based ring-oscillator. The reliability of the proposed circuit is calculated, which came out to be thehighest at 0.7V supply and 16nm process node for a 10% deviation in operating parameters. Also, the process parametervariation of leakage power, delay, and PDP of the proposed circuit came out to be proper and stable thus maintaining thefunctionality of the proposed circuit.

Ultra-Low-Power FinFETs-Based TPCA-PUF Circuit for Secure IoT Devices.

Low-power and secure crypto-devices are in crucial demand for the current emerging technology of the Internet of Things (IoT). In nanometer CMOS technology, the static and dynamic power consumptions are in a very critical challenge. Therefore, the FinFETs is an alternative technology due to its superior attributes of non-leakage power, intra-die variability, low-voltage operation, and lower retention voltage of SRAMs. In this study, our previous work on CMOS two-phase clocking adiabatic physical unclonable function (TPCA-PUF) is evaluated in a FinFET device with a 4-bits PUF circuit complexity. The TPCA-PUF-based shorted-gate (SG) and independent-gate (IG) modes of FinFETs are investigated under various ambient temperatures, process variations, and ±20% of supply voltage variations. To validate the proposed TPCA-PUF circuit, the QUALPFU-based Fin-FETs are compared in terms of cyclical energy dissipation, the security metrics of the uniqueness, the reliability, and the bit-error-rate (BER). The proposed TPCA-PUF is simulated using 45 nm process technology with a supply voltage of 1 V. The uniqueness, reliability, and the BER of the proposed TPCA-PUF are 50.13%, 99.57%, and 0.43%, respectively. In addition, it requires a start-up power of 18.32 nW and consumes energy of 2.3 fJ/bit/cycle at the reference temperature of 27 °C.

Design of low-power and high-speed CNTFET-based TCAM cell for future generation networks

In network routers and lookup tables for fast searching, ternary content addressable memories (TCAMs) have found great use. For future generation networks, architecture is essential for efficient TCAM in terms of power consumption and speed of service. A TCAM cell with an optimized CNTFET is proposed in this paper. The TCAM cell proposed is designed for improved performance using optimized CNTFET with shorted gate (SG) CNTFET and independent gate CNTFET (IG-CNTFET). As access transistors, IG-CNTFETs are used in the SRAM cell design, and SG-CNTFETs are used in the comparison circuit. The 4 × 4 TCAM array was also planned using the TCAM cells proposed. The suggested CNTFET TCAM cell and array showed better performance than that of TCAM cells and arrays based on CMOS and FinFET. The suggested CNTFET-based TCAM with SG shows a substantial improvement in search delay and average power and peak power compared to CMOS and FinFET-based cell technology. Compared to CMOS and FinFET technologies, the average capacity of the proposed TCAM cell is substantially enhanced. The proposed technique's search delay is enhanced by 17.2 percent over TCAM cell based on FinFET. Compared to the FinFET and CMOS-based TCAM cell, the peak power of the proposed technique is also enhanced. All the simulations are carried out at 32 nm with HSPICE technology.

Snapback-free shorted anode LIGBT with controlled anode barrier and resistance* *Project supported by the National Natural Science Foundation of China (Grant Nos. 61604027 and 61704016) and the Fund from Chongqing Technology Innovation and Application Development (Key Industry Research and Development), China (Grant No. cstc2018jszx-cyzd0646).

A novel shorted anode lateral-insulated gate bipolar transistor (SA LIGBT) with snapback-free characteristic is proposed and investigated. The device features a controlled barrier V barrier and resistance R SA in anode, named CBR LIGBT. The electron barrier is formed by the P-float/N-buffer junction, while the anode resistance includes the polysilicon layer and N-float. At forward conduction stage, the V barrier and R SA can be increased by adjusting the doping of the P-float and polysilicon layer, respectively, which can suppress the unipolar mode to eliminate the snapback. At turn-off stage, the low-resistance extraction path (N-buffer/P-float/polysilicon layer/N-float) can quickly extract the electrons in the N-drift, which can effectively accelerate the turn-off speed of the device. The simulation results show that at the same V on of 1.3 V, the E off of the CBR LIGBT is reduced by 85%, 73%, and 59.6% compared with the SSA LIGBT, conventional LIGBT, and TSA LIGBT, respectively. Additionally, at the same E off of 1.5 mJ/cm2, the CBR LIGBT achieves the lowest V on of 1.1 V compared with the other LIGBTs.

Design space exploration of low-power flip-flops in FinFET technology

As technology evolves, new devices emerge to overcome the known short-channel effects of conventional MOSFETs. FinFETs, as recent devices, are widely used in modern processor designs. Elaborate design of circuit elements can effectively increase the overall chip performance. In this paper we studied the design of high performance flip-flop (FF) using FinFET devices. We have investigated several transistor sizing methods in FinFET technology to design the FF circuit based on different input and output capacitances. The results indicate that the circuit designed using minimum-energy-delay-area product (min-EDAP) approach has the lowest PDP. We developed a modified logical effort approach that leads to a minimum EDP design compared to the other approaches. The performance of flip-flop is also investigated based on the metrics extracted from energy efficient curve (EEC). Results show that the ED metric has the minimum EDP in all cases. Moreover, the E4D metric shows the least variations against frequency and voltage fluctuations, while the ED4 metric is more robust against temperature variations. Simulations are performed using HSPICE in 16 nm FinFET technology with shorted-gate (SG) mode configuration.

Design and analysis of INDEP FinFET SRAM cell at 7‐nm technology

AbstractThe reduction in size of metal oxide semiconductor (MOS) devices results in increase in leakage power dissipation, which occurs due to the short‐channel effects in subthreshold region. Now a day's power dissipation is one of the crucial issues that the modern electronic industry is facing. Fin‐type field‐effect transistor (FinFET) can be proven as a best substitute to reduce leakage power dissipation in logic circuits. Degradation of performance with process variations is of major concern and needs to design FinFET circuits with minimum leakage power dissipation. In this paper, static random‐access memory (SRAM) cell is designed using low power shorted‐gate (SG) FinFETs at 7‐nm technology to minimize leakage power dissipation besides improving other performance parameters like static noise margins (SNMs) and power delay product (PDP) as well. The various parameters are analyzed using butterfly and N‐curve methods. The ASAP7 PDK is used to design SRAM cells using Cadence Virtuoso tool. The simulated results show that FinFET input‐dependent (INDEP) technique reduces the leakage power dissipation by 32.08% and 13.50%, respectively, in read and write conditions of FinFET SRAM cell. The Monte‐Carlo simulation results show the reduction in average power using INDEP approach at ±10% process, voltage and temperature (PVT) variations under 3σ Gaussian distribution of FinFET SRAM cell.

Stacking Techniquefor Low Power Sram

Static random access memory leakage current is becoming one of the critical issues for low-power systems. SRAM-based FinFET Double Gate has become a better option for profound submicron techniques owing to its better short channel effect. In this work, we review some of the leakage current sources and low power reduction technique to reduce leakage. As animprovement of our research work,6T SRAM memory cells can be implemented using independent gate FinFET which gives lower leakage as well as better performance over the shorted gate FinFET mode. This is also implemented using stacking technique to decrease leakage. Therefore, the power devoured by the different SRAM cells is likened with the Tanner tool in 45 nm technique.

Effective Low Leakage 6T and 8T FinFET SRAMs: Using Cells With Reverse-Biased FinFETs, Near-Threshold Operation, and Power Gating

Power gating is commonly used to reduce leakage current in SRAM memories; leakage current has a large impact on SRAM energy consumption. We first focus on power gating FinFET SRAMs and then evaluate three techniques to reduce the leakage power and energy-delay product (EDP) of six- and eight-transistor (6T, 8T) FinFET SRAM cells. We compare the EDP savings obtained using: 1) power gating FinFETs; 2) near-threshold operation at $V_{\mathrm{ DD}}=0.6$ V instead of the nominal $V_{\mathrm{ DD}}=1$ V; and 3) alternative SRAM cells with shorted gate (SG) and low power (LP) configured FinFETs; LP-configuration reverse-biases a FinFET’s back gate and reduces leakage current by up to 97%. SRAM cells with higher leakage benefit the most from power gating since they see the largest reductions in leakage current. Sharing power gating transistors among multiple SRAM cells can lead to more leakage current savings, but causes slower read and write speeds which can diminish their effectiveness. Alternative SRAM cells with lower leakage benefit the most from near-threshold operation to further reduce leakage current. Near-threshold operation and/or power gating reduces the 6T SG FinFET SRAM scheme’s EDP slightly more than using the 8T SG FinFET SRAM scheme, but using an LP 8T SRAM scheme, such as LP_INV1.2, with near-threshold operation is more effective than power gating and provides the largest reductions in EDP. The design techniques recommended by this brief can enable longer battery life for small sensor systems and thus greater reliability for Internet-of-Things (IoT) devices.

Design of FinFET Based Self-Biased OTA for Low Power Applications

This work explores the design of an Operational Trans conductance Amplifier (OTA) using Independent Gate (IG) FinFET. For the different configurations of FinFET such as IG, Low Power (LP) and Shorted Gate (SG), optimal gm and ro values have been found. FinFET devices are used to increase the performance by reducing the power dissipation as the front and back gate voltages are controlled independently. The designed three stage FinFET based OTA operates at 0.5 V power supply and achieves gain of 64 dB, 33 phase margin and 20 MHz unity gain frequency. The proposed OTA circuit is tested in Cadence virtuoso with FinFET 32nm BSIM-CMG model.

Low power FinFET content addressable memory design for 5G communication networks

Content Addressable Memories (CAMs) are used in diverse applications, such as network protocols used in Wireless Sensor Networks (WSN), text analytics, reconfigurable computing and signal processing applications that require ultra-high speed and very low power consumption. In this work, a novel FinFET CAM using PMOS access transistors, based on PTM–MG transistor models in 22 nm and 14 nm technology is analyzed. Simulation results show that the Independent Gate (IG) FinFET CAM using PMOS access transistor exhibits a 38% improvement in the speed and 48% power consumption reduction compared to the shorted gate (SG) CAM based on 22 nm technology. Similarly, the proposed IG cell achieves a 5% improvement in speed and 50% reduction in power consumption when 14 nm technology is adopted. Hence the proposed IG cell in 14 nm has 6% improvement in speed and 59% less power consumption over 22 nm technology which is suitable for modern 5th generation communication networks.

Full-Wave Bridge Rectifier with CMOS Pass Transistors Configuration

An effortless, more efficient full-wave bridge rectifier is introduced with minimum distortion. Efficient and exploratory combinations of CMOS logic are not only utilized to design full-wave bridge rectifier, but also as pass transistors configurations at the input. The particular CMOS logic (used to design core rectifier circuit) is a collective form of SDG-NMOS and SGS-PMOS. SDG-NMOS refers to a shorted drain gate n-channel metal oxide semiconductor. SGS-PMOS refers to shorted gate to source p-channel metal oxide semiconductor. Due to the utilization of renovated MOS configuration after the replacement of the diode, the efficiency of the full-wave bridge rectifier is increased up to 11% compared to p-n junction diode based full wave bridge rectifier. The proposed full wave bridge rectifier is a comparably low power circuit. The proposed CMOS based full-wave bridge rectifier is optimized at 45-nm CMOS technology. Cadence experimental simulation and implementations of the leakage power and efficiency demonstrate better consistency through the proposed circuit.

Low power schmitt trigger based sram using 32nm finfet devices

In this work we propose a novel Schmitt Trigger FinFET SRAM cell. The proposed SRAM cell is focused on high noise immunity and low static leakage, the cell uses two modified Schmitt Trigger based inverters in cross coupled manner. Use of Schmitt Trigger in place of inverters improves noise margin and read performance of the cell. The proposed cell uses FinFET devices in shorted gate and independent gate modes, helping in achieving low static leakage. The proposed SRAM cell shows considerable improvement in performance in terms of SNM, static power consumption and read/write delays due to its modified structure.

Full-VDD and near-threshold performance of 8T FinFET SRAM cells

We evaluate full-VDD and near-threshold operation of nine novel eight-transistor (8T) FinFET SRAM cell schemes using shorted gate (SG) and low power FinFET configurations for 32-bit by 1024-word SRAMs. 8T SRAM schemes outperform six-transistor schemes since SG-configured read FinFETs minimize delay and reverse-biased inverter FinFETs’ back gates reduce leakage current by up to 97%. At near-threshold, 8T FinFET cell delay increases by 56%, but leakage current and energy-delay product (EDP) decrease by up to 16% and 77%, respectively. 8T Low-Power Inverters scheme uses these configurations and reduces EDP by 60% (79% at near-threshold) versus the conventional SG 8T FinFET SRAM.

Design of Ternary Content-Addressable Memories with Dynamically Power-gated Storage Cells Using FinFETs

An independent-gate FinFET can operate in two modes: SG (shorted-gate) and IG (independent-gate) modes, and thus a FinFET-based circuit offers rich design options for lower power, better performance or reduced transistor count. In this paper, we present two novel dynamically power-gated FinFET TCAM cells, called DPG-17T and DPG-16T, which power-gate the prefix data storage unit when storing a ‘don't care’ value. With the dynamic power-gating mechanism, DPG 17T/DPG-16T achieve lower power dissipation by eliminating the switching power of the comparison FinFETs and suppressing the leakage power of the prefix data storage when storing a ‘don't care’ value. Moreover, the discharge path of the matchline in DPG-17T/DPG-16T can be constructed with only one FinFET instead of two FinFETs, greatly boosting the search speed. Simulation results have shown that a TCAM of 64-word×128-bit using DPG-17T/DPG-16T can reduce the worst-case search delay by 53.0%/53.6% and improve the energy-delay product by 68.5%/70.4% when operating under a search rate of 4.0 GHz.

Ultra-Low-Leakage and High-Performance Logic Circuit Design Using Multiparameter Asymmetric FinFETs

Recently, multigate field-effect transistors have started replacing traditional planar MOSFETs to keep pace with Moore’s Law in deep submicron technology. Among different multigate transistors, FinFETs have become the preferred choice of the semiconductor industry owing to low fabrication cost, superior performance, lower leakage, and design flexibility. The back and front gates of a FinFET can either be shorted or remain independent, leading to two modes of operation: Shorted-Gate (SG) and Independent-Gate (IG). For a given mode of operation, the physical parameters of the FinFET can either be symmetric or asymmetric in nature. In this article, for the first time, we analyze multiparameter asymmetric SG FinFETs and illustrate their potential for implementing logic gates and circuits that are both ultra-low-leakage and high-performance simultaneously. We restrict this work to SG devices because IG FinFETs (symmetric/asymmetric) suffer from severely degraded on-current, which makes them unattractive for high-performance designs. We first compare head-to-head all viable single- and multiparameter symmetric/asymmetric SG FinFETs. Among all such FinFETs, the traditional SG (which are symmetric in nature), Asymmetric Workfunction Shorted-Gate (AWSG), and Asymmetric Workfunction-Underlap Shorted-Gate (AWUSG) FinFETs show the most promise. We characterize these devices under process variations in gate length ( L G ), fin thickness ( T SI ), gate-oxide thickness ( T OX ), gate underlap ( L UN ), and gate-workfunction (Φ G ) as well as supply voltage ( V DD ) variations, followed by a gate-level leakage/delay analysis at different temperatures. Although AWSG FinFETs consume very low leakage power, they do suffer from performance degradation relative to SG FinFETs. Similarly, our study reveals that no other single-parameter asymmetric FinFET provides a good combination of low-power and high-performance design. We show that gates/circuits based on AWUSG FinFETs are faster, yet consume much less leakage power and less area than gates/circuits based on traditional SG FinFETs. We observe 53.4% (30.2%) maximum (average) reduction in total power at temperature T = 348 K while meeting the same delay constraint, with 14.2% (13.5%) reduction in area for AWUSG circuits relative to SG circuits. At T = 373 K , we see 68.6% (46.9%) maximum (average) reduction in total power.

McPAT-PVT: Delay and Power Modeling Framework for FinFET Processor Architectures Under PVT Variations

As technology has moved into the deep-submicrometer regime, the shrinking feature size has placed a considerable stress on CMOS fabrication due to short-channel effects (SCEs) and excessive leakage. Although many research efforts have been devoted to seeking system-level solutions, underlying transistor-level solutions are still urgently required to overcome these obstacles. FinFETs have emerged as promising substitutes for conventional CMOS due to their superior control of SCEs and process scalability. However, FinFETs still face lithographic and workfunction engineering challenges, in addition to those posed by supply voltage and temperature variations across the integrated circuit (IC). These lead to process, supply voltage, and temperature (PVT) variations in FinFET ICs, which, in turn, lead to large spreads in delay and leakage. In this paper, we present a multicore power, area, and timing (McPAT)-PVT, an integrated framework for the simulation of power, delay, as well as PVT variations of FinFET-based processors. McPAT-PVT uses a FinFET design library, consisting of logic and memory cells, to model circuit-level characteristics as well as their PVT variation trends. It is based on macromodels, derived from very accurate TCAD device simulations that characterize various functional units in a processor under PVT variations, making yield analysis for timing and power for processor components possible. McPAT-PVT can model both shorted-gate (SG) and asymmetric-workfunction shorted-gate (ASG) FinFET-based processors. Combining these macromodels with a FinFET-based CACTI-PVT cache model and an ORION-PVT on-chip network model, McPAT-PVT is able to simulate a delay and power consumption of all processor components under PVT variations. We present extensive simulation results to demonstrate its efficacy, including for an alpha-like processor and multicore simulations based on Princeton Application Repository for Shared-Memory Computers benchmarks. Results show that the ASG FinFET-based processor implementation has $73\times $ lower leakage power and $2.6\times $ lower total power relative to the SG FinFET-based processor implementation for the same performance, with <1% area penalty.

Modelling and simulation of FinFET circuits with predictive technology models

During analysis of complexities of the Metal Oxide Semiconductor Field Effect Transistors (MOSFET) technology to obtain the adequate gate control above the channel, FinFET technology founded on Double or Multiple gate (more than two gates) arrangement is improved technology alternative for auxiliary lessening the size of the MOSFET. In favor of double or dual gate MOSFET (DG MOSFET) the gate control above the channel that formed in between source and drain terminal efficiently. As a result the numerous short channel effects like sub-threshold swing, Drain Induced Barrier Lowering (DIBL-effect), gate leakage current, punch through etc. do not include growing of carrier concentration addicted to the channel. This paper is devoted to specific explanation on the subject of the DG MOSFET composition with its exacting kind termed the same as FinFET technology. FinFET technology has four modes such as shorted-gate (SG) mode, low power (LP) mode, independent-gate (IG) mode and hybrid IG/LP mode and performed the comparative analysis of stand-by leakage (when the circuit is idle), delay, total power consumption and noise of the circuit, using Cadence Virtuoso tool at 45 nm.

Accurate Leakage/Delay Estimation for FinFET Standard Cells under PVT Variations using the Response Surface Methodology

Among different multi-gate transistors, FinFETs and Trigate FETs have set themselves apart as the most promising candidates for the upcoming 22nm technology node and beyond owing to their superior device performance, lower leakage power consumption, and cost-effective fabrication process. Innovative circuit design and optimization techniques will be required to harness the power of multi-gate transistors, which in turn will depend on accurate leakage and timing characterization of these devices under spatial and environmental variations. Hence, in order to aid circuit designers, we present accurate analytical models using central composite rotatable design (CCRD) based on response surface methodology (RSM) to estimate the leakage current and delay of FinFET standard cells under the effect of variations in gate length ( L G ), fin thickness ( T SI ), gate-oxide thickness (T OX ), gate-workfunction (Φ G ), supply voltage ( V DD ), and temperature ( T ). To the best of our knowledge, this is the first such attempt to develop analytical models for leakage/delay estimation of FinFET logic gates. To derive these models, we employ TCAD device simulations of adjusted 2D device cross sections that have been shown to track TCAD device simulations of 3D device behavior within a 1--3% error range. This drastically reduces the CPU time of our modeling technique (by several orders of magnitude) without much loss in accuracy. We present analytical leakage and delay models for different sizes and logic styles (e.g., shorted-gate (SG) and independent-gate (IG) FinFETs at the 22nm technology node). Both leakage and delay estimates derived from the analytical models are in close agreement with quasi-Monte Carlo (QMC) simulation results (QMC simulations track the accuracy of Monte Carlo simulations, but are several orders of magnitude faster) obtained for different adjusted-2D logic gates with a root mean square error (RMSE) in the 0.23%--5.87% range.

Ultra-low-leakage chip multiprocessor design with hybrid FinFET logic styles

FinFET has begun replacing CMOS at the 22nm technology node because of its enhanced ability to mitigate short-channel effects. Although leakage power of FinFET logic gates is lower than their CMOS counterparts, it still contributes to a large part of total power consumption. In this article, we show how ultra-low-leakage FinFET chip multiprocessors (CMPs) can be designed using a hybrid logic style. This hybrid style exploits the ultra-low-leakage feature of asymmetric-workfunction shorted-gate (ASG) FinFETs and the high-performance feature of shorted-gate (SG) FinFETs. We explore the impact of the hybrid style at both the module and CMP levels. To do this, we have developed FinFET logic libraries targeted at SG and ASG logic gates, suitably characterized for various parameters of interest. We have also modified existing tools and created a framework to evaluate the hybrid designs of SRAMs, caches, and CMPs. Using the design with SG FinFETs as the baseline for comparison, our experimental results show that the hybrid style can reduce leakage power of execution units to as low as 10.6% of the baseline without hurting performance, that of SRAMs to between 21.5% and 4.8% of the baseline with 0%-8.3% delay overhead, and that of CMPs to 10.0% of the baseline with negligible performance degradation.