Full-VDD and near-threshold performance of 8T FinFET SRAM cells

Abstract

We evaluate full-VDD and near-threshold operation of nine novel eight-transistor (8T) FinFET SRAM cell schemes using shorted gate (SG) and low power FinFET configurations for 32-bit by 1024-word SRAMs. 8T SRAM schemes outperform six-transistor schemes since SG-configured read FinFETs minimize delay and reverse-biased inverter FinFETs’ back gates reduce leakage current by up to 97%. At near-threshold, 8T FinFET cell delay increases by 56%, but leakage current and energy-delay product (EDP) decrease by up to 16% and 77%, respectively. 8T Low-Power Inverters scheme uses these configurations and reduces EDP by 60% (79% at near-threshold) versus the conventional SG 8T FinFET SRAM.