Shorted Gate Research Articles

Performance Evaluation of 14 nm FinFET‐Based 6T SRAM Cell Functionality for DC and Transient Circuit Analysis

As the technology node size decreases, the number of static random‐access memory (SRAM) cells on a single word line increases. The coupling capacitance will increase with the increase of the load of word line, which reduces the performance of SRAM, more obvious in the SRAM signal delay and the SRAM power usage. The main purpose of this study is to investigate the stability and evaluate the power consumption of a 14 nm gate length FinFET‐based 6T SRAM cell functionality for direct current (DC) and transient circuit analysis, namely, in resistor‐capacitor (RC) delay. In particular, Berkeley Short‐channel IGFET Model‐Common Multigate (BSIM‐CMG) model is utilized. The simulation of the SRAM model is carried out in HSPICE based on 14 nm process technology. A shorted‐gate (SG) mode FinFET is modeled on a silicon on insulator (SOI) substrate. It is tested in terms of functionality and stability. Then, a functional SRAM is simulated with 5 GHz square wave at the input of word line (WL). Ideal square wave and square wave with 100 RC, 5 RC, 1 RC, and 0.5 RC are asserted to the WL and the bit lines (BL&BLB) of SRAM. Voltage at node q and is observed. The simulation shows that 1 RC is the minimum square wave that will store correct value in node q and node . Thus, this discovery from the research can be used as a modeling platform for circuit designers to explore and improve the SRAM tolerance against RC delay.

Schmitt Trigger Based SRAM Using FinFET Technology- Shorted gate mode

Schmitt Trigger Based SRAM Using FinFET Technology- Shorted gate mode

Design of Logic Gates and Flip-Flops in High-Performance FinFET Technology

With the emergence of nonplanar CMOS devices at the 22-nm node and beyond, it is highly likely that multigate device adoption will occur in a high-performance process technology, owing to the increased performance and area benefits. In this paper, for the first time, we evaluate symmetric (Symm-Φ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> ) and asymmetric (Asymm-Φ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> ) gate-workfunction FinFETs head to head in a high-performance process, using technology computer-aided design 3-D device simulations. We demonstrate that Asymm-Φ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> shorted-gate (a-SG) n/p-FinFETs, which use both workfunctions corresponding to typical high-performance metal-gate n/p-FinFETs, are promising, as they can yield over two orders of magnitude lower leakage without excessive degradation in ON-state current, in comparison to Symm- ΦG shorted-gate (SG) FinFETs, placing them in a better position than back-gate biased independent-gate (IG) FinFETs for leakage reduction. Thereafter, we explore the design space of FinFET logic gates, latches, and flip-flops, for optimal tradeoffs in leakage versus delay and temperature, using mixed-mode 2-D device simulations. Elementary logic gates (such as INV, NAND2, NOR2, XOR2, and XNOR2) using Asymm-Φ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> SG-mode FinFETs appear to be located optimally in the leakage-delay spectrum, in comparison to the most versatile configurations possible by mixing corresponding Symm-Φ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> SG- and IG-mode FinFETs. Latches and flip-flops, however, require an astute combination of Symm-Φ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> and Asymm-Φ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> FinFETs to optimize leakage, delay, and setup time simultaneously.

Analysis and design of low power SRAM cell using independent gate FinFET

Scaling of bulk MOSFET faces great challenges in nanoscale integration technology by producing short channel effect which leads to increased leakage. FinFET has become the most promising substitute to bulk CMOS technology because of reducing short channel effect. Dual-gate FinFET can be designed either by shorting gates on either side for better performance or both gates can be controlled independently to reduce the leakage and hence power consumption. A six transistor SRAM cell based on independent-gate FinFET technology is described in this paper for simultaneously reducing the active and standby mode power consumption. A work is focused on the independent gate FinFET technology as this mode provides less power consumption, less area consumption and low delay as compared to other modes. Leakage current and power consumption in independent gate FinFET is compared with tied gate or shorted gate FinFET SRAM cell. Moreover, delay has been estimated in presented SRAM cells. Further, leakage reduction technique is applied to independent gate FinFET 6T SRAM cell.

CMOS compatible shorted anode auxiliary cathode lateral insulated gate bipolar transistors

The performance of CMOS-compatible, shorted-anode, auxiliary-cathode lateral insulated gate bipolar transistors (SA-ACLIGBT), fabricated using a standard 2.5- mu m high-voltage integrated circuit process, is investigated. Typical on-state current densities of more than 240 A/cm/sup 2/ at a gate voltage of 10 V and a forward voltage of 5 V have been obtained. These devices show a latchup-free, current saturation behavior when compared to equivalent shorted-anode LIGBTs. Measured high-voltage turnoff characteristics of the SA-ACLIGBT are superior to those of the conventional SA-LIGBT. These results confirm that by including an auxiliary cathode and extending a p/sup +/ buried layer from under the p well into the drift region of the SA-LIGBT structure, the holes flowing into the p well can be diverted to improve device performance. The auxiliary cathode plays a vital role in preventing the triggering of the parasitic thyristor; it also plays an important role in extracting minority carriers during the turnoff transient.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Analysis of negative differential resistance in the I-V characteristics of shorted-anode LIGBT's

The physical mechanism responsible for the negative differential resistance (NDR) in the current-voltage characteristics of the shorted anode lateral insulated gate bipolar transistor (SA-LIGBT) is explained through two-dimensional numerical simulation. The NDR regime is an inherent feature of all SA-LIGBTs, and results from the two different conduction mechanisms responsible for current flow in the device. These conduction mechanisms are minority-carrier injection and majority-carrier flow. Since both the anode geometry and the doping profile control the onset and the degree of minority-carrier injection, the effect these parameters have on the NDR is investigated. A simple lumped-element equivalent model of the SA-LIGBT allows qualitative predictions to be made on how changes in the device geometry and doping profiles influence the NDR regime. It is shown that conductivity modulation is a necessary but not sufficient condition for the occurrence of negative resistance in SA-LIGBT devices. Also required is a large voltage drop in the high-resistivity drift region before conductivity modulation is initiated. This causes small changes in the anode current level, greatly decreasing the total resistance across the drift region.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Today's plasma etch chemistries : Peter H. Singer. Semiconductor int., 68 (March 1988)

We evaluate full-VDD and near-threshold operation of nine novel eight-transistor (8T) FinFET SRAM cell schemes using shorted gate (SG) and low power FinFET configurations for 32-bit by 1024-word SRAMs. 8T SRAM schemes outperform six-transistor schemes since SG-configured read FinFETs minimize delay and reverse-biased inverter FinFETs’ back gates reduce leakage current by up to 97%. At near-threshold, 8T FinFET cell delay increases by 56%, but leakage current and energy-delay product (EDP) decrease by up to 16% and 77%, respectively. 8T Low-Power Inverters scheme uses these configurations and reduces EDP by 60% (79% at near-threshold) versus the conventional SG 8T FinFET SRAM.

Study of Shorted Gate Type Silicon Controlled Rectifier

Study of Shorted Gate Type Silicon Controlled Rectifier

Early Effect SCR and its Application for Shorted Gate Type

Early Effect SCR and its Application for Shorted Gate Type