Model For Short-channel MOSFETs Research Articles

Characterization and compact modeling of short channel MOSFETs at cryogenic temperatures

This paper presents an overall characterization, physics-based device analysis, and compact modeling of a commercial 110nm bulk CMOS technology. I−V measurements and DC parameters extraction are performed on low threshold voltage (low VTH, LVT) and regular VTH (RVT) devices with various geometry dimensions from 300 K to 6 K. Different levels of improvement of subthreshold swing (SS), OFF-state current (IOFF), and mobility indicates the potential to optimize the performance of circuits at cryogenic temperatures. However, the temperature characteristics of the mobility and series resistance show a great dependence on the channel length of the devices, which complicates the calculation of the ON-state current at cryogenic temperatures. Moreover, VTH roll-off caused by short channel effect (SCE) get worse, which can be attributed to the increased bulk Fermi potential (ϕf). These channel-length-related effects add extra challenges to the design of cryogenic circuits. An optimized compact model based on BSIM4 is proposed to capture the device characteristics at 6 K, which can produce accurate simulation results only through parameter configuration rather than model equation modification and has been applied to the design of cryogenic CMOS circuits.

Corrections to “Design-Oriented All-Regime All-Region 7-Parameter Short-Channel MOSFET Model Based on Inversion Charge”

In the above article <xref ref-type="bibr" rid="ref1" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">[1]</xref> , <xref ref-type="disp-formula" rid="deqn33-deqn36" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">equations (33)</xref> and <xref ref-type="disp-formula" rid="deqn33-deqn36" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">(36)</xref> had a typing error. The correct equations are:

Design-Oriented All-Regime All-Region 7-Parameter Short-Channel MOSFET Model Based on Inversion Charge

Design-Oriented All-Regime All-Region 7-Parameter Short-Channel MOSFET Model Based on Inversion Charge

A Short-Channel &lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$I$ &lt;/tex-math&gt; &lt;/inline-formula&gt;–&lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$V$ &lt;/tex-math&gt; &lt;/inline-formula&gt; Model for 2-D MOSFETs

This paper presents an analytic $I$ – $V$ model for short-channel MOSFETs made of 2-D semiconductor material. First, a subthreshold current model is formulated based on the solutions to 2-D Poisson’s equation with negligible mobile charge. Next, a velocity saturation model is developed under the framework of a drift and diffusion long-channel model. These two models are then unified into an all region, short-channel $I$ – $V$ model with both drain induced barrier lowering and velocity saturation effects. Ballistic currents, including the intraband tunneling and the above-the-barrier transport, have been examined and compared with the thermionic currents.

A novel surface potential-based short channel MOSFET model for circuit simulation

In this paper a novel analytical approximation method for surface potential (ψs) calculation in compact MOSFET model is presented. It achieves excellent accuracy and good calculation speed over all regions from accumulation to strong inversion. With this approximation method, a surface potential-based compact model for short channel MOSFET is developed. Comparison with measured data is also presented to validate the new model.

An analytical channel thermal noise model for deep-submicron MOSFETs with short channel effects

In this work, an analytical channel thermal noise model for short channel MOSFETs is derived. The transfer function of the noise was derived by following the Tsividis’ method. The proposed model takes into account the channel length modulation, velocity saturation, and carrier heating effects in the gradual channel region. Modeling results show good agreements with the measured noise data.

A threshold voltage model for short-channel MOSFETs taking into account the varying depth of channel depletion layers around the source and drain

In this paper, an analytical model for threshold voltage of short-channel MOSFETs is presented. For such devices, the depletion regions due to source/drain junctions occupy a large portion of the channel, and hence are very important for accurate modeling. The proposed threshold voltage model is based on a realistic physically-based model for the depletion layer depth along the channel that takes into account its variation due to the source and drain junctions. With this, the unrealistic assumption of a constant depletion layer depth has been removed, resulting in an accurate prediction of the threshold voltage. The proposed model can predict the drain induced barrier lowering (DIBL) effect and hence, the threshold voltage roll-off characteristics quite accurately. The model predictions are verified against the 2-D numerical device simulator, DESSIS of ISE TCAD.

A subthreshold surface potential model for short-channel MOSFET taking into account the varying depth of channel depletion layer due to source and drain junctions

An analytical subthreshold surface potential model for short-channel MOSFET is presented. In this model, the effect of varying depth of the channel depletion layer on the surface potential has been considered. The effect of the depletion layers around the source and drain junctions on the surface potential, which is very important for short channel devices is included in this model. With this, the drawback of the existing models that assume a constant channel depletion layer thickness is removed resulting in a more accurate prediction of the surface potential. A pseudo-two-dimensional method is adopted to retain the accuracy of two-dimensional analysis yet resulting in a simpler manageable one-dimensional analytical expression. The subthreshold drain current is also evaluated utilizing this surface potential model.

2-D threshold voltage model for short-channel MOSFET with quantum-mechanical effects

A threshold condition different from the classical one is proposed for MOSFET with quantum effects, by means of self-consistent numerical solution of the Schrdinger's and Poisson's equations, and thus an accurate 1-D threshold-voltage model is obtained with good agreements between simulated results and measurement data. Based on this 1-D model, an accurate 2-D quantum-modified threshold-voltage model for small-scale MOSFET is developed by solving the quasi-2D Poisson's equation and taking short-channel effects and quantum-mechanical effects into consideration. The model can also be used for simulation of electrical properties and design of structural parameters for deep-submicron MOSFETs with high-k materials as gate dielectric.

Efficient frequency-domain simulation technique for short-channel MOSFET

This paper proposes and investigates a short-channel MOSFET model down to a 0.1-/spl mu/m regime for the frequency-domain analysis of the device operation through the harmonic balance technique. The efficiency and the preciseness of our method are validated by comparison of simulation results with the two-dimensional time-domain simulation tool, MEDICI. Along with the carrier transport model, the displacement current components are included in the terminal current equations for the extended analysis under external circuit environments.

Complete high-frequency thermal noise modeling of short-channel MOSFETs and design of 5.2-GHz low noise amplifier

Taking a velocity saturation effect and a carrier heating effect in the gradual channel region, complete thermal noise modeling of short-channel MOSFETs including the induced gate noise and its correlation coefficients is presented and verified extensively with experimentally measured data. All of the four noise models have excellently predicted experimental data with maximal error less than 10% for the deep-submicron MOSFETs. Using these models and a simultaneous matching technique for both optimal noise and power, a low noise CMOS amplifier optimized for 5.2-GHz operation has been designed and fabricated. Experiments using an external tuner show that both NF/sub 50/ and NF/sub min/ are very close to 1.1 dB, which is an excellent figure of merit among reported LNAs.

Drain current thermal noise modeling for deep submicron n- and p-channel MOSFETs

The drain current thermal noise has been measured and modeled for the short-channel devices fabricated with a standard 0.18 μm CMOS technology. We have derived a physics-based drain current thermal noise model for short-channel MOSFETs, which takes into account the velocity saturation effect and the carrier heating effect in gradual channel region. As a result, it is found that the well-known Qinv/L2––formula, previously derived for long-channel, remains valid for even short-channel. The model excellently explained the carefully measured drain thermal noise for the entire VGS and VDS bias regions, not only in the n-channel, but also in the p-channel MOSFETs. Large excess noise, which was reported earlier in some other groups, was not observed in both the n-channel and the p-channel devices.

A new drain current model for short-channel MOSFETs

Reduction of channel length makes the channel current to be less than that of drain current. In this paper, by using multiplication factor model [Proc. IEEE IRPS. (1996) 318, Proc. IEEE IRPS (1999) 167] and a simple approximation of the collector current of PBT the drain current in short-channel MOSFETs is modeled and simulated. This model makes use of four parameters, which by extracting them for each device, it is possible to calculate total drain current. The simulation results from this model are compared with the results obtained from MINIMOS, in which match observed between them.

A simple subthreshold swing model for short channel MOSFETs

A new approach to calculate the subthreshold swing of short channel bulk and silicon-on-insulator metal oxide semiconductor field effect transistors is presented. The procedure utilizes a channel-potential expression appropriate for submicron dimensions. The final result is similar to that used for long channels except for a factor λ which represents the short channel effects. Comparison with different published results reveals excellent quantitative agreement.

An analytical model of simultaneous switching noise in CMOS systems

An accurate and analytical model for simultaneous switching noise (SSN) on ground lines in CMOS circuits is presented. This model can compute SSN for the case where only some drivers switch and the others remain quiet, that is, the model considers the loading effects on the quiet drivers. It was confirmed that the proposed model is more accurate than the existing ones through HSPICE simulation using the level 28 model for short-channel MOSFETs. The proposed model can provide useful design guides for CMOS driver circuits.

An analytical physical model for short-channel MOSFETs

In the light of a modified two-dimensional Poisson equation, an analytical model for the threshold voltage Vth of deep-submicrometre MOSFETs is developed, which can show Vth's nonlinear dependence on drain voltage Vds. Meanwhile, by introducing a normalized effective gate voltage Vgtx to obtain continuous channel charge characteristics from the subthreshold to the strong inversion region and properly including major small-geometry and high-field effects such as carrier velocity saturation, DIBL, field dependent mobility, inversion layer capacitance and channel-length modulation etc, an accurate, continuous and scaled-down drain current physical model Ids is obtained. The model's output for channel length L = 0.26-0.8 µm fits both the experimental data and MINIMOS simulation well in all operation regions, and is available for VLSI simulation and reliability applications.

Modeling of saturation transconductance for short-channel MOSFETs

By considering several secondary effects including the channel length modulation, mobility degradation, drain induced barrier lowering, and threshold voltage variation, an accurate saturation transconductance model for short-channel MOSFETs is developed. The calculated values of saturation transconductance agree well with the BSIM3 simulation results and the experimental results for devices with effective channel length in the range of 0.44-10 μm. This model has the advantages of less number of model parameters and can be used to analyze the small signal performance of analog circuits.

An improved quasi two-dimensional model for short-channel MOSFETs

An improved quasi two-dimensional model for the electric field in the drain region, and its subsequent application in the modeling of the strong-inversion region current, the drain conductance, and the substrate current for a short-channel MOSFET are presented in this paper. This work also considers the variation of the surface potential as a function of the gate bias beyond strong-inversion, and the variation of the lateral electric field as a function of depth into the bulk, in addition to the other second-order effects accounted for in the literature. These two additional modifications resulted in a continuous drain conductance curve with respect to the drain-to-source voltage at the onset of saturation point, which is a significant contribution of this work. Previous work attributed this discontinuity to the modeling of drain/source series resistance as lumped elements, which our work shows to be not entirely correct. A simple method is proposed to calculated the drain conductance. The model is also used to obtain the substrate current by numerically integrating the electric field in the pinch-off region without introducing any extra fitting parameter.

Analytical theory of two-dimensional charge sheet model for short channel MOSFETs under non linear charge control

An analytical theory of two-dimensional charge sheet model of short channel IGFETs under non-linear charge control which geometrically takes into account the two-dimensional edge effect is developed. This theory includes the effects of non-uniform doping and uses the charge sheet model approach. Since the diffusion current plays an important role in subthreshold and saturation regions, the model also takes it into account along with the drift current. The model thus proposed is more accurate than the earlier models as it includes the effects of diffusion and leads to an exact analytical expression for the device current. The results obtained are compared with those of uniform doping. It is found that the current magnitude starts out greater for non-uniform doping and as the gate voltage is increased, the increase in current slows down and approaches to that of uniform doping.

Transit-time model for short-channel MOSFET's

A new analytical transit-time model for submicrometer MOS devices has been developed. The model is based on a modified SPICE level-three MOSFET DC model, and it allows the use of a physical value for the charge carrier saturation velocity. This is essential for accurate transit-time modeling. Both DC and transit-time models show good agreement with the results obtained from more complicated two-dimensional numerical simulations. >