Model For Short-channel MOSFETs Research Articles

An improved analytical short-channel MOSFET model valid in all regions of operating for analog/digital circuit simulation

An improved analytical model for short-channel MOSFETs which is valid in all regions of operation with both the continuous drain current and the output conductance by introducing a source-drain series resistance dependent scaling factor is proposed for analog/digital circuit simulation. This model considers all second-order effects for an accurate determination of the pinchoff point location without internal numerical iterations. Comparisons with experimental data for submicron devices confirm the model validity. Furthermore, a simple interpolation is also presented to maintain the continuous slope of the output conductance and its effect on the drain current is demonstrated to be acceptable.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

An improved analytical model for short-channel MOSFETs

An analytical model for short-channel MOSFETs including all second-order effects is proposed with a significant improvement on the saturation region operation. This model requires no numerical iterations and describes channel-length modulations of submicrometer MOS devices more accurately than other existing models. In addition, the influence of both the source-drain resistance and short-channel effects on the lateral channel electric field is also investigated.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

An analytical CMOS inverter delay model including channel-length modulations

An analytical delay model of a CMOS inverter that includes channel-length modulation and source-drain resistance as well as high-field effects is introduced. This model is based on the improved short-channel MOSFET model derived from a quasi-two-dimensional analysis of operation in the saturation region. Calculations of the rise, fall, and delay times show good agreement with SPICE MOS level three simulations. >

A charge sheet capacitance model of short channel MOSFETs for SPICE

An analytic charge sheet capacitance model for short-channel MOSFETs is derived and implemented in SPICE. It is based on a surface potential formulation which computes the approximate surface potential without iterations. The DC current, charges, and their first and second derivatives are continuous under all operating regions. Equations for node charges are derived to guarantee charge conservation. Short-channel effects such as velocity saturation, channel-length modulation, and channel-side-fringing-field capacitances are included in the model equations. The model shows good agreement with the measured gate capacitance for long- and short-channel MOSFETs. The SPICE simulation of a ring oscillator using this model shows the significant variation of circuit performance due to the short-channel effects on capacitances.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A physics based analytical MOSFET model with accurate field dependent mobility

A new approach to the modeling of short-channel MOSFETs in the triode region is proposed. A system of equations for an accurate quasi-1-D-formulation of the current transport in MOSFETs is presented. A highly accurate description of the local normal effective field-dependent surface mobility is included. The mobility degradation due to the parallel field is modeled by a hyperbolic formula for P-channel and by Jaggi's expression for N-channel MOSFETs. The mobility models are examined by comparing with several experimental data. The system includes a precise modeling of the inversion layer charge and surface potential, and it is valid in both weak and strong inversion. Using novel approaches an approximate solution in the triode region is derived analytically. The obtained expressions for the current are explicit. An error analysis of the analytical current models is carried out by comparing with a numerical solution of the starting quasi-1-D-formulation. As a result of the error analysis the simplest final expression for the drain current is proposed. Some further extensions of the model are noted.

A charge-based capacitance model of short-channel MOSFETs

A quasi-static two-dimensional intrinsic capacitance model for short-channel MOSFETs is discussed. It is derived based in a physically based charge-sharing scheme and implemented using a quasi-static solution of a MOS device simulator. Two-dimensional field-induced mobility degradation, velocity saturation, and short-channel effects are included in the model. The charge conservation rule holds, and channel charge partitioning is properly treated. The simulation results clearly show the importance of two-dimensional field-induced effects to short-channel MOS devices. Comparison of the simulated results with experimentally measured data shows that the model is far more reliable than the analytical one. The method can be used to link a device simulator and a circuit simulator for accurate timing calculation in both digital and analog MOS integrated circuits. >

Parameter extraction method for inhomogeneous MOSFETs locally damaged by hot carrier injection

We present a simple analytical model for short channel MOSFETs locally degraded by hot electron injection. This model gives a good qualitative description of the interaction between the defective and defect-free channel regions in the ohmic regime. Working on this model, we propose a parameter extraction method which provides a useful characterization of the resulting physical damage. The length of the damaged region as well as the density of the created defects and the carrier mobilities in both parts of the channel are obtained from strong inversion conductance mesurements while the nature of these defects is deduced from weak inversion measurements. The validity of our method is evaluated by means of a 2-D simulator and is proved to be good in a wide range of situations.

Simple two-sections model for short channel MOS transistors in saturation

The paper presents a model for short channel MOSFETs based on a new empirical formula for the drain current in saturation. The model guarantees the continuity of the transconductance, the output conductance and its derivatives at the transition from the triode to the saturation region, while taking into account some important second-order effects. The theoretical predictions of the model are found to be in excellent agreement with experimental data.

MOSLAP???A Circuit Simulation Program for Teaching Short-Channel MOS Circuit Design

The current approach to teaching MOS circuit design is based on the classic square-law MOSFET device model. This model is capable of adequately modeling long-channel devices; however, current levels of technology are providing short-channel MOS devices which exhibit significant second-order effects which cannot be accounted for by the square-law model. Due to inherent increases in model complexity, the need arises for the use of computers to aid in designing MOS circuits containing short-channel devices. Presented here is MOSLAP (MOS loadline analysis program), a new interactive circuit simulation tool for teaching short-channel MOS circuit design. MOSLAP contains a complete short-channel MOSFET model, and is capable of analyzing general MOS circuits. MOSLAP can perform dc analysis, small-signal ac analysis, dc transfer function analysis, and can generate various loadlines for visual inspection of dc operating point information. This last feature makes MOSLAP unique.

Performance of heterostructure FET's in LSI

This paper reports a comparative evaluation of circuits based on heterostructure field-effect transistors (HFET's) for delay, noise-margin and power dissipation in unloaded and loaded configurations. n-channel enhancement/depletion (E/D) circuits operating at 300 and 77 K and complementary circuits operating at 77 K are compared with respect to each other. The paper also shows that a modified short-channel MOSFET model gives good agreement with experimental behavior of the devices and is adequate for evaluation. Fan-in (FI) sensitivities of delay are much smaller than fan-out (FO) sensitivities of delay for E/D circuits because of capacitive effects. E/D circuit delays are more fan-out sensitive at 300 K than at 77 K because of lower current capability. The fan-in sensitivity of the delay of complementary circuits is larger and is comparable to that circuit's fan-out sensitivity. Under loaded conditions (FI is 3, FO is 3, capacitance is 0.1 pF) at 77 K, 0.5-µm gate length E/D structures show gate delays near 50 ps and 1.0-µm gate length show gate delays near 75 ps. The circuits at 300K exhibit a doubling of the gate delay. The complementary circuits offer, at 77 K, a performance of 70 ps at 0.5-µm gate length and 140 ps at 1.0-µm gate length. The significant performance improvements of complementary circuits with reduction of gate lengths to submicrometer dimensions occurs primarily due to reduction in the device capacitances and secondarily due to improvement of current characteristics. They demonstrate noise margins that are more than 50 percent better than their E/D counterpart along with lower power dissipations. The larger noise margin may be a significant advantage because the small logic swings require stringent parasitic resistance and threshold voltage control.

An analytic threshold-voltage model for short-channel enhancement mode n-channel MOSFETs with double boron channel implantation

This paper presents an analytic threshold-voltage model for n-channel MOSFETs with double boron channel implantation, in which the implanted boron profile in the substrate is approximated by a triple-step profile. The surface potential at strong inversion has been calculated from the condition of equal rate change of depletion layer charge density and inversion layer charge density with respect to the surface potential. The built-in voltage of the high-low junction in a triple-step profile has been correctly included in calculating the surface potential and maximum depletion width at strong inversion. This consideration removes the discontinuities of the threshold voltage with respect to the applied back-gate bias as the maximum depletion width passes through the high-low junction. Based on the above considerations, an analytic threshold-voltage model for short-channel MOSFETs with a triple-step profile in the substrate has been developed by using the modified charge sharing scheme. The geometric factors of the charge sharing scheme have been incorporated into the developed threshold-voltage model by means of the depletion charge superposition which also guarantees continuous threshold voltage change as the back-gate bias is continuously applied. Moreover, the developed threshold-voltage model has been compared with the experimental results of fabricated devices. Satisfactory agreement between these comparisons has been obtained for wide ranges of effective channel lengths and back-gate biases.

A simple punchthrough voltage model for short-channel MOSFET's with single channel implantation in VLSI

Based on the step-profile approximation and geometrical analysis, the punchthrough voltage of short-channel enhancement n-channel MOSFET's with single channel implantation has been derived by defining a punchthrough depth. The punchthrough depth, which represents the distance of the two-dimensional potential ridge from the SiO 2 -Si interface, is calculated by the surface potential of the punchthrough point. Therefore, the derived punchthrough voltage model is then analytically expressed in terms of device geometries and implant parameters. Comparisons between the developed model and the experimental devices have been made and excellent agreement has been obtained.

A simple punchthrough model for short-channel MOSFET's

Punchthrough currents impose severe limitations on the minimum channel length and leakage currents of scaled MOS transistors. A simple model is proposed to calculate the low-level punchthrough characteristics. Taking into account the two-dimensional geometrical effects, this model calculates the drain-induced barrier-lowering (DIBL) and the punchthrough current as a function of the processing parameters, and the gate, drain, and substrate bias. Experiments on devices with substrate dopings 6 × 1014and 6.6 × 1015cm-3and channel lengths from 1 to 2 µm show good agreement with the theory.

An analytical breakdown model for short-channel MOSFET's

Avalanche-induced breakdown mechanisms for short-channel MOSFET's are discussed. A simple analytical model that combines the effects due to the ohmic drop caused by the substrate current and the positive feedback effect of the substrate lateral bipolar transistor is proposed. It is shown that two conditions must be satisfied before breakdown will occur. One is the emission of minority carriers into the substrate from the source junction, the other is sufficient avalanche multiplication to cause significant positive feedback. Analytical theory has been developed with the use of a published model for short-channel MOSFET's. The calculated breakdown characteristics agree well with experiments for a wide range of processing parameters and geometries.

IIB-2 two-dimensional charge-sheet model for short-channel MOSFETs

IIB-2 two-dimensional charge-sheet model for short-channel MOSFETs

A calibrated model for the subthreshold operation of a short channel MOSFET including surface states

Describes a simple two-dimensional subthreshold model for short channel MOSFET's. The effects of surface state density are also included in the model. A regional charge density approximation was used in the solution of Poisson's equation and an analytical solution of the continuity equation in two dimensions was derived. Excessive computations are avoided in the present model; this was made possible by the use of a valid regional charge approximation. The model was experimentally verified by performing measurements on short channel devices. The model was calibrated from measurements on a long channel device which was present on the same silicon chip. Results are presented for the subthreshold leakage current as a function of substrate bias, polysilicon gate length, diffusion depth and surface state density.

A simple model for short channel MOSFET's

A model for short channel MOSFET's is presented. The model is simple in spite of taking 2-dimensional (2-D) effects into account. Predicted I-V characteristics are in good agreement with experimental results. This model can be utilized in circuit analysis programs.