An analytical CMOS inverter delay model including channel-length modulations

Hwang-Cherng Chow Hwang-Cherng Chow,Wu-Shiung Feng Wu-Shiung Feng

doi:10.1109/4.149422

An analytical CMOS inverter delay model including channel-length modulations

Hwang-Cherng Chow Hwang-Cherng Chow, Wu-Shiung Feng Wu-Shiung Feng

https://doi.org/10.1109/4.149422

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Journal: IEEE Journal of Solid-state Circuits	Publication Date: Jan 1, 1992
Citations: 19

Affiliation: National Taiwan University

#Analytical Delay Model #Source-drain Resistance + Show 8 more

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Abstract

An analytical delay model of a CMOS inverter that includes channel-length modulation and source-drain resistance as well as high-field effects is introduced. This model is based on the improved short-channel MOSFET model derived from a quasi-two-dimensional analysis of operation in the saturation region. Calculations of the rise, fall, and delay times show good agreement with SPICE MOS level three simulations. >

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