Abstract
An analytical delay model of a CMOS inverter is introduced for the first time which includes channel-length modulation, source-drain resistance and high-field effects. Calculations of the rise, fall and delay times show good agreement with SPICE simulations.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
