Short-channel MOS Transistors Research Articles

SIMULATION OF DRAIN DEPTH EFFECT ON PARASITIC CURRENTS IN FLASH-MEMORY CELLS.

In present paper the drain depth effect on parasitic currents in Flash-memory cells based on short-channel MOS-transistors has been calculated by using Monte Carlo simulation of electron drift in such devices. It is shown that the increase of the drain depth leads to the decrease of the value of parasitic tunnel current. It takes place because for deep drain electron current density in the transistor channel is shifted into substrate.

Three-Port Model of a Modern MOS Transistor in Millimeter Wave Band, Considering Distributed Effects

Distributed nature of an MOS transistor becomes significant in high frequencies, especially in the millimeter wave band. Two types of distributed effects are encountered in an MOS transistor: the distributed effect along the transistor channel, referred as nonquasi static (NQS) effect, and the distributed effect along the gate finger. We denote the former as lateral distributed effect and the later as longitudinal distributed effect (LDE). Lateral distributed effect has been studied in many works and has been considered either accurately or approximately in the available MOS small-signal models. However, LDEs have not accurately been accounted for, except for few works in which an MOS transistor has been analyzed using transmission line approach to derive two-port ${Y}$ parameters of the transistor. Unfortunately, the two-port distributed model is not useful when the transistor is used in common gate, common drain, or cascode configurations. In this paper, we have developed a new three-port distributed model of an MOS transistor to accurately capture the LDEs. Furthermore, the proposed model can be used in conjunction with new Berkeley short-channel IGFET model (BSIM) radio frequency (RF) small-signal models, such as BSIM4.7 and BSIM6. To evaluate the proposed model, we have used Taiwan Semiconductor Manufacturing Company 90 nm RF-CMOS technology parameters. Our results show that LDE is considerably more significant than NQS effect in millimeter wave band, in the case of a short channel MOS transistor with long gate finger. This reveals the importance of LDEs in RF MOS transistor models, especially in millimeter wave band applications.

A Unified Channel Thermal Noise Model for Short Channel MOS Transistors

A unified channel thermal noise model valid in all operation regions is presented for short channel MOS transistors. It is based on smooth interpolation between weak and strong inversion models and consistent physical model including velocity saturation, channel length modulation, and carrier heating. From testing for noise benchmark and comparing with published noise data, it is shown that the proposed noise model could be useful in simulating the MOSFET channel thermal noise in all operation regions.

Hot-carrier reliability and breakdown characteristics of multi-finger RF MOS transistors

Hot-carrier reliability and drain breakdown characteristics of multi-finger short channel MOS transistors are studied in detail. Several abnormal characteristics were observed. With the aid of numerical simulation, we found that the shared drain and source regions for adjacent gate fingers can lead to current crowding and result in the finger number-dependent current-voltage characteristics. In addition, the high current density spots near the drain region would result in the significant hot-carrier induced transconductance degradation as well as remarkable drain breakdown voltage lowering.

Performance Boost Using a New Device Structure Design for SOI MOSFETs Beyond 25nm Node

We demonstrate that very high performance ultra short-channel MOS transistors can be realized in accumulation mode SOI MOSFETs benefited from device structure with higher current drivability and a good suppression of degradation resulted from the gate electrode depletion. Furthermore, we reveal that the short channel effect is suppressed in accumulation mode devices by thinning the SOI layer and BOX thicknesses with both the polysilicon gate electrode and metal gate.

A surface potential based subthreshold drain current model for short-channel MOS transistors

Utilizing the concept of the splitting of the quasi-Fermi energy on the surface, a surface potential based subthreshold drain current model for the short-channel MOS transistor is presented. Both the drift and diffusion components are considered in this model. The model is based on an accurate surface potential model that takes into account the varying depth of the channel depletion layer around the source and drain junction which is very important for short-channel devices. The model predictions are compared with the predictions by the 2D numerical device simulator DESSIS, and a very good agreement is obtained.

Direct experimental verification of shot noise in short channel MOS transistors

Drain noise current was measured at an extended temperature range on n-MOS transistors of various lengths made in a 0.18 urn process. A comparison with theoretical noise models strongly indicates t ...

Effect of Technology Scaling on MOS Transistor Performance with High-K Gate Dielectrics

AbstractThe impact of technology scaling on the MOS transistor performance is studied over a wide range of dielectric permittivities using two-dimensional (2-D) device simulations. It is found that the device short channel performance is degraded with increase in the dielectric permittivity due to an increase in dielectric physical thickness to channel length ratio. For Kgate greater than Ksi, we observe a substantial coupling between source and drain regions through the gate dielectric. We provide extensive 2-D device simulation results to prove this point. Since much of the coupling between source and drain occurs through the gate dielectric, it is observed that the overlap length is an important parameter for optimizing DC performance in the short channel MOS transistors. The effect of stacked gate dielectric and spacer dielectric on the MOS transistor performance is also studied to substantiate the above observations.

Simulation of 2D quantum effects in ultra-short channel MOSFETs by a finite element method

This paper presents a flexible numerical technique which is especially suited to analyze lateral modulation of quantum effects in short channel MOS transistors. We discuss boundary conditions for the Schrodinger equation and the impact of the finite element meshing. We show how channel length shortening alters the sub-band structure, thus giving an evaluation of the limits of a 1D quantum approach.

Characterization of Series Resistances and Mobility Attenuation Phenomena in Short Channel MOS Transistors

As the scaling proceeds, the transverse electric field increase, and a mobility attenuation phenomenon becomes of primordial interest. Indeed, the high transverse electric field is generally ascribed [1] to surface roughness scattering in the channel and consequently reduce effective mobility of carriers. In short channel MOSFET, the Source-Drain resistance Rsd influence strongly the effective mobility.The aim of this work is therefore to propose an original method especially conceived for the extraction of the series resistance Rsd. Using the approach of the Surface Roughness Scattering which enables a consistent modelling of the mobility to be obtained from low to high electric field [2], this allow to determine all model parameters in particular a Series Resistance from the plot of the transfer characteristic drain current Idversus gate voltage Vg Curves.

Overlooked interfacial silicide-polysilicon gate resistance in MOS transistors

We discuss a previously overlooked gate resistance (R/sub g/) component in silicided polysilicon-gate metal-oxide-semiconductor field-effect-transistors (MOSFETs). Since the high-frequency properties depend critically on R/sub g/, this has motivated the recent addition of a resistive gate input in the BSIM3v3 MOSFET model. Our TLM results show that the contact resistance between silicide and polysilicon, built into the gate of a typical MOSFET, is of the same magnitude as the silicide sheet resistance. This contact resistance affects model scaling and will dominate R/sub g/ in narrow-width and short-channel MOS transistors.

Simultaneous switching noise analysis and low-bounce buffer design

An accurate equation to estimate simultaneous switching noise (SSN) created by CMOS output buffers is proposed. This analytic equation includes the carrier velocity saturation effects of a short-channel MOS transistor. Simulation results show that the proposed closed-form equation estimates the SSN precisely and the error is below 10% as compared with HSPICE simulation results. Design procedures of a low-bounce tapered buffer which take SSN into consideration are also proposed. Several output buffer design examples are demonstrated to show the significant improvement of the low-bounce buffer design. A test chip of the output buffer is implemented to operate at 400 MHz and the measurement results match the design specifications.

The effect of random dopant fluctuations on the minimum channel length of short-channel MOS transistors

The minimum channel length of a MOS transis- tor which can be achieved while keeping the fluctuations of the threshold voltage caused by random fluctuations of dopant atoms in the depletion layer within a tolerable range is exam- ined. As the basis of all calculations, the Poisson distribution which is used to describe the number of dopant atoms in the depletion layer is combined with an analytical model for the threshold voltage of a short-channel transistor. The influence of major technological parameters on the minimum channel length is presented in detail by fitting a polynomial equation to the calculated data.

Punchthrough currents in sub-micron short channel MOS transistors

The punchthrough current in sub-micron MOS transistors is essentially initiated at the surface near the edge of source junction. A surface diffusion current ( I sdif) originates from the injection of minority carriers from the source junction due to the combined effect of drain-induced-barrier-lowering (DIBL) and surface-band-bending ( Δφ so). The DIBL effect increases with decreasing channel length. In addition, the extracted Δφ so from the punchthrough current indicates that surface space charges at the source edge shift from the accumulation/depletion mode for long sub-micron devices (≈0.62 μm) to the strong-inversion mode for deep sub-micron devices (≈0.12 μm). For intermediate sub-micron devices (≈0.37 μm), I sdif eventually converts to the bulk space-charge-limited current ( I scl) as the connected source/drain depletion region expands with increasing drain bias. For long sub-micron devices only I sdif dominates, while for deep sub-micron devices it converts rapidly to I scl in the bulk depletion regions over the drain bias range investigated.

A comprehensive submicrometer MOST delay model and its application to CMOS buffers

In this paper, an accurate delay model for MOS transistors in submicrometer CMOS digital circuits is presented. It takes into account a ramp shape input voltage and a feedforward capacitive coupling between gate and drain nodes, along with the main second-order effects present in short-channel MOS transistors. The proposed model shows an average agreement with SPICE simulations of 3% in the calculation of the propagation time, tested on a minimum inverter with a 0.7-/spl mu/m CMOS reference technology for a wide range of input voltage slopes. An example of application in optimization algorithms regarding CMOS tapered buffers is also reported. A maximum error ranging from 3-6% with respect to SPICE has been found for the optimized circuits.

Two dimensional analytical modelling of short channel MOS transistors

An analytical model for the current–voltage characteristics of short channel MOS transistors is presented. The model is a two dimensional model based on the solution of a Poisson equation in the depletion region under the gate. The degradation of inversion carriers’ mobility due to the strong lateral electric field is taken into account. An attractive feature of this model is that it provides an analytical expression for the I–V characteristics of the MOSFET as a function of material and device parameters. In addition it is valid for both short- and long- channel transistors. The numerical I–V characteristics obtained using the proposed model are in close agreement with experimental data. It is concluded that the proposed model is an accurate and efficient model. Consequently it can be used in circuit simulation programs

Impact of anomalous short-channel MOS transistors on VLSI circuit reliability

In VLSI and ULSI circuits, a major reliability concern is that completed, fully functional, in-specification integrated circuits may contain one or more anomalous transistors with substantially closer source-to-drain spacing than the minimum-design-rule devices, and that such transistors will be more susceptible to degradation or failure due to hot-carrier effects, total-dose-radiation effects or other instabilities. A further concern is that such vulnerable transistors will not be detected during conventional electrical testing or during typical high-reliability integrated circuit burn-in procedures such as static or dynamic burn-in at 125°C, since hot carrier effects tend to anneal out at elevated temperatures, as well as having a negative temperature acceleration factor. Experimental studies have shown that fully functional nMOS transistors with shorter-than-normal channel lengths can have many orders of magnitude greater susceptibility to hot-electron-induced threshold voltage shifts, compared to transistors with minimum-design-rule dimensions of 1.2μm. Total-dose radiation tests showed that anomalous n-channel MOS transistors can have orders-of magnitude higher post-total-dose radiation leakage than nominal devices made by the same process. Several possible types of screening techniques that can be considered for detecting integrated circuits containing anomalous transistors are discussed, including a low-dissipation dynamic stress test at room temperature or at −55°C, with parts electrically characterized before and after the stress test. A large change (delta) of certain critical parameters would be used to predict future failure. Quiescent CMOS supply-current testing could also be used to detect the presence of anomalous transistors in some types of integrated circuits.

A generalized tanh law MOSFET model and its applications to CMOS inverters

A generalized tanh law model is proposed to simulate the current-voltage characteristics of both long-channel and short-channel MOS transistors. The proposed model is used to calculate the propagation delay, short-circuit power dissipation, and logic threshold voltage of CMOS inverters. The results obtained are in good agreement with those obtained using classical models. >

Physical mechanism of the “reverse short-channel effect” in MOS transistors

The threshold voltage of short-channel-length MOS transistors may increase as the channel length of the device is decreased. This phenomenon is due to the existence of a potential barrier at the edge of the channel to the source/drain junction. This model was demonstrated experimentally with the drain current and the transconductance vs gate-voltage characteristics of short-channel length MOS transistors. It is shown that a potential barrier can strongly degrade the performance of MOS transistors.

New method for assessment of depletion charge dependence of mobility in short-channel silicon MOS transistors

An original method for the extraction of the depletion charge mobility dependency coefficient α based on the exploitation of the body-to-gate transconductance ratio gb/gm(Vg) MOSFET characteristics is presented. This method allows the demonstration of the fact that α is a parameter strongly dependent on channel length for both device types (p or n). Moreover, it is shown that the channel length reduction of a is closely correlated to that of the depletion charge to the gate oxide capacitance ratio Cd/Cox due to the increase of charge sharing effect when scaling down the devices.