Short-channel MOS Transistors Research Articles

Potential and Carrier Concentration Distributions in MOS Transistors at Punch-Through

A two-dimensional (2D) model of an MOS transistor based on a complete set of steady-state transport equations is described. The model proposed enables a detailed analysis of punch-through in short-channel MOS transistors. By means of numerical solution of this model, the potential and carrier concentration distributions as well as current density distributions in the gate region are determined. It is shown that punch-through in MOS transistors does not take place at the silicon surface but in the bulk and the current densities along individual layers parallel to the SiSiO2 interface are not constant. This nature of punch-through is caused by the “surface accumulation wedge” which exist between the drain and source depletion region under the gate. The influence of the design parameters and supply voltages on the location and dimensions of the “accumulation wedge” is demonstrated. [Russian Text Ignored].

Electrical characteristics of a DSA MOS transistor with a fine structure

Fabrication technologies and electrical characteristics of a diffusion self-aligned MOS transistor (DSA MOST) or a double-diffused MOS transistor (DMOST) are discussed in comparison with a conventional short-channel MOS transistor as a fundamental device for a VLSI. The symmetrical DSA MOS LSI with enhancement depletion configurations requires six photolithographic steps and the number of the steps is the same as that of an NMOS LSI with small physical dimensions. The only difference is the step orders of the enhancement channel doping in these devices. The lowering effects of the threshold voltage and the source drain breakdown voltage are smaller in the DSA MOST than in the conventional MOS transistor.

Electrical characteristics of a DSA MOS transistor with a fine structure

Fabrication technologies and electrical characteristics of a diffusion self-aligned MOS transistor (DSA MOST) or a double-diffused MOS transistor (DMOST) are discussed in comparison with a conventional short-channel MOS transistor as a fundamental device for a VLSI. The symmetrical DSA MOS LSI with enhancement depletion configurations requires six photolithographic steps and the number of the steps is the same as that of an NMOS LSI with small physical dimensions. The only difference is the step orders of the enhancement channel doping in these devices. The lowering effects of the threshold voltage and the source drain breakdown voltage are smaller in the DSA MOST than in the conventional MOS transistor. The drain current I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</inf> of the symmetrical DSA MOS transistor is, respectively, 1.13 (in the nonsaturation region) and 1.33 (in the saturation region) times larger than that of the conventional short-channel NMOS transistor at the effective gate voltage of 3.0 V. The improvement of the short-channel effect, the current voltage characteristics, and the power-delay product are obtained by the scaling of the DSA MOS transistor.