Shallow Trench Isolation Research Articles

A new guard ring for radiation induced noise reduction in photodiodes implemented in 0.18 μm CMOS technology

A new p-type guard ring by introduction of a thin p-type layer which encloses shallow trench isolation (STI) layer is utilized to reduce radiation induced noise in photodiodes implemented in 0.18 $$\upmu$$ m standard complementary-metal-oxide-semiconductor (CMOS) technology. The guard ring efficiency is characterized according to a new radiation model developed for p–n photodiodes implemented in the same technology. The extracted model which is the oxide trapped charges and interface state values is verified using a simulation setup for two different structures. The optimized guard ring with the doping concentration of $$10^{+19}$$ atoms cm $$^{-3}$$ reduces the dark current of photodiodes at 1 Mrad dose of ionizing radiation from $$6.97\,\times \,10^{-13}$$ A (without the guard ring) to $$1.29\,\times \,10^{-14}$$ A for STI in contact with the active region structure and from $$5.95\,\times \,10^{-13}$$ A (without the guard ring) to $$2\,\times \,10^{-14}$$ A for STI surrounded p-well structure. The proposed guard ring can be used as a promising structure for ionizing radiation hardening of photodiodes.

Total Ionizing Dose Response of Different Length Devices in 0.13 μm Partially Depleted Silicon-on-Insulator Technology**Supported by the Weapon Equipment Pre-Research Foundation of China under Grant No 9140A11020114ZK34147, and the Shanghai Municipal Natural Science Foundation under Grant Nos 15ZR1447100 and 15ZR1447200.

An anomalous total dose effect that the long length device is more susceptible to total ionizing dose than the short one is observed with the partially depleted silicon-on-insulator technology. The measured results and 3D technology computer aided design simulations demonstrate that the devices with different channel lengths may exhibit an enhanced reverse short channel effect after radiation. It is ascribed to that the halo or pocket implants introduced in processes results in non-uniform channel doping profiles along the device length and trapped charges in the shallow trench isolation regions.

Quantitative Electron Energy Loss Spectroscopy (EELS) Analysis of Flowable CVD Oxide for Shallow Trench Isolation of finFET Integration

Journal Article Quantitative Electron Energy Loss Spectroscopy (EELS) Analysis of Flowable CVD Oxide for Shallow Trench Isolation of finFET Integration Get access J Li, J Li IBM Research, Albany, NY 12203 Email: juntaoli@us.ibm.com, Tel: (518) 292-7419 Search for other works by this author on: Oxford Academic Google Scholar J Bruley, J Bruley IBM Research, Yorktown Heights, NY 10598 Search for other works by this author on: Oxford Academic Google Scholar R Conti, R Conti IBM Research, Albany, NY 12203 Search for other works by this author on: Oxford Academic Google Scholar M Belyansky, M Belyansky IBM Research, Albany, NY 12203 Search for other works by this author on: Oxford Academic Google Scholar S Metha, S Metha IBM Research, Albany, NY 12203 Search for other works by this author on: Oxford Academic Google Scholar J Strane, J Strane IBM Research, Albany, NY 12203 Search for other works by this author on: Oxford Academic Google Scholar L Tai, L Tai IBM Systems, Hopewell Junction, NY 12533 Search for other works by this author on: Oxford Academic Google Scholar L Jiang, L Jiang IBM Research, Albany, NY 12203 Search for other works by this author on: Oxford Academic Google Scholar J Demarest, J Demarest IBM Research, Albany, NY 12203 Search for other works by this author on: Oxford Academic Google Scholar J Gaudiello, J Gaudiello IBM Research, Albany, NY 12203 Search for other works by this author on: Oxford Academic Google Scholar ... Show more Y Zhu, Y Zhu IBM Research, Yorktown Heights, NY 10598 Search for other works by this author on: Oxford Academic Google Scholar A Grill A Grill IBM Research, Yorktown Heights, NY 10598 Search for other works by this author on: Oxford Academic Google Scholar Microscopy and Microanalysis, Volume 23, Issue S1, 1 July 2017, Pages 1462–1463, https://doi.org/10.1017/S1431927617007978 Published: 04 August 2017

Analysis and optimization of RC delay in vertical nanoplate FET

In this paper, we have analyzed short channel effects (SCEs) and RC delay with Vertical nanoplate FET (VNFET) using 3-D Technology computer-aided design (TCAD) simulation. The device is based on International Technology Road-map for Semiconductor (ITRS) 2013 recommendations, and it has initially gate length (LG) of 12.2nm, channel thickness (Tch) of 4nm, and spacer length (LSD) of 6nm. To obtain improved performance by reducing RC delay, each dimension is adjusted (LG=12.2nm, Tch=6nm, LSD=11.9nm). It has each characteristic in this dimension (Ion/Ioff=1.64×105, Subthreshold swing (S.S.)=73mV/dec, Drain-induced barrier lowering (DIBL)=60mV/V, and RC delay=0.214ps). Furthermore, with long shallow trench isolation (STI) length and thick insulator thickness (Ti), we can reduce RC delay from 0.214ps to 0.163ps. It is about a 23.8% reduction. Without decreasing drain current, there is a reduction of RC delay as reducing outer fringing capacitance (Cof). Finally, when source/drain spacer length is set to be different, we have verified RC delay to be optimum.

Effect of contact-etch-stop-layer and Si1-xGex channel mechanical properties on nano-scaled short channel NMOSFETs with dummy gate arrays

The layout effect influences the performance of nanoscale devices with advanced strain engineering, considering that the size of a technology node continuously shrinks to ≤20nm. Transistors with a long gate width could be fabricated, and the portion that protrudes outside the channel region could be located on a soft shallow trench isolation region and even across the dummy active region of diffusion. Induced strained silicon technology should be considered when managing and enhancing mobility gain in devices with narrow channel widths. Thus, we fabricated a 20nm silicon-based n-type metal-oxide-semiconductor field-effect transistor with a Si0.75Ge0.25 alloy channel and a+3.0GPa tensile contact etch stop layer as stressors. The transistor was utilized at different dummy gate arrays and dummy poly pitches. The fabricated device was subjected to oriented stress simulation, and the relationship between the piezoresistance effect and the stress component within the device channel was investigated. The best performance, which was 40% higher than that of conventional transistors, was observed in the transistor with 100nm gate width.

Influences of silicon-rich shallow trench isolation on total ionizing dose hardening and gate oxide integrity in a 130 nm partially depleted SOI CMOS technology

The influences of silicon-rich shallow trench isolation (STI) on total ionizing dose (TID) hardening and gate oxide integrity (GOI) in a 130nm partially depleted silicon-on-insulator (SOI) complementary metal-oxide semiconductor (CMOS) technology are investigated. Radiation-induced charges buildup in STI oxide can invert the parasitic sidewall channel of the n-channel transistor, which will increase the off-state leakage current and decrease the threshold voltage for the main transistor. Compared with the general STI process, the silicon-rich STI process can significantly suppress the increase in leakage current and negative shifts in subthreshold region induced by the total dose radiation, implying TID hardening for STI trench oxide. However, the silicon-rich STI process has a deleterious impact on GOI. It leads to the thin gate oxide thickness at trench corner and lowers the gate oxide breakdown voltage. Issues of gate oxide integrity induced by silicon-rich STI are investigated in this paper, and an optimized process to solve this problem is proposed and examined. Finally, the TID response of the optimized silicon-rich STI process is presented in comparison to the general and silicon-rich STI processes.

(Invited) Gate-All-Around Transistors Based on Vertically Stacked Si Nanowires

Gate-all-around (GAA) transistors based on vertically stacked horizontal nanowires are promising candidates to replace FinFETs in future CMOS technology nodes. First of all, GAA devices provide optimal electrostatic control over semiconducting nanowire channels, which enables downscaling of the gate length to below the FinFET limit, while maintaining low off-state leakage [1]. Besides, horizontally oriented nanowires are an evolutionary extension of FinFETs, as opposed to vertical nanowires which require more disruptive technology and design changes [2]. Finally, stacking of nanowires is relevant for enhancing the drive current per footprint. Based on these considerations, GAA transistors made of vertically stacked horizontal nanowires have been included in the ITRS roadmap to reduce the contacted gate pitch, which is a key figure of merit for CMOS device density, to below ~40 nm in 2019-2021 [3]. In the context of the industrial relevance described above, we present the fabrication of Si GAA devices on bulk Si substrates. Multiple processing aspects that are relevant for bulk CMOS technology definition are addressed, including stacking of 8-nm-diameter Si wires at 45-nm lateral pitch and 20-nm vertical pitch [4], and nanowire-compatible replacement metal gate processing in combination with threshold voltage tuning by dual work function metal integration [5]. Temperature restrictions for the formation of shallow trench isolation, and the interaction between N- and P-type junction formation on one hand and nanowire release processes on the other hand are discussed as well. [1] K. J. Kuhn, IEEE Trans. Electron Devices, vol. 59 (7), p.1813, (2012). [2] L. Liebmann et al., VLSI Tech. Dig., p.112 (2016). [3] The International Roadmap for Semiconductors (ITRS) 2.0, http://www.itrs2.net/ (2015). [4] H. Mertens et al., VLSI Tech. Dig., p.158 (2016). [5] H. Mertens et al., IEDM Tech. Dig., p.524 (2016). Figure 1

Layout Effects on High Frequency and Noise Parameters in MOSFETs

<p>This study reviews related studies on the impact of the layout dependent effects on high frequency and RF noise parameter performances, carried out over the past decade. It specifically focuses on the doughnut and multi- finger layouts. The doughnut style involves the polygonal and the 4- sided techniques, while the multi-finger involving the narrow-oxide diffusion (OD) and multi-OD. The polygonal versus 4-sided doughnut, and the narrow-OD with multi-fingers versus multi-OD with multi- fingers are reviewed in this study. The high frequency parameters, which are of concern in this study, are the cut- off frequency (f<sub>T</sub>) and the maximum frequency (f<sub>MAX</sub>), whereas the noise parameters involved are noise resistance (R<sub>N</sub>) and the minimum noise figure (NF<sub>min</sub>). In addition, MOSFET parameters, which are affected by the layout style that in turn may contribute to the changes in these high frequency, and noise parameters are also detailed. Such parameters include transconductance (G<sub>m</sub>); gate resistance (R<sub>g</sub>); effective mobility (μ<sub>eff</sub>); and parasitic capacitances (c<sub>gg</sub> and c<sub>gd</sub>). Investigation by others has revealed that the polygonal doughnut may have a larger total area in comparison with the 4- sided doughnut. It is also found by means of this review that the multi-finger layout style with narrow-OD and high number of fingers may have the best performance in f<sub>T</sub> and f<sub>MAX</sub>, owing partly to the improvement in G<sub>m</sub>, μ<sub>eff</sub>, c<sub>gg</sub>, c<sub>gd</sub> and low frequency noise (LFN). A multi-OD with a lower number of fingers may lead to a lower performance in f<sub>T</sub> due to a lower G<sub>m</sub>. Upon comparing the doughnut and the multi-finger layout styles, the doughnuts appeared to perform better than a standard multi-finger layout for f<sub>T</sub>, f<sub>MAX</sub>, G<sub>m</sub> and μ<sub>eff</sub> but are poorer in terms of LFN. It can then be concluded that the narrow-OD multi-finger may cause the increase of c<sub>gg</sub> as the transistor becomes narrower, whereas a multi-OD multi-finger may have high R<sub>g</sub> and therefore may lead to the increase of f<sub>T</sub> and f<sub>MAX</sub> as the transistor becomes narrower. Besides, the doughnut layout style has a higher G<sub>m</sub> and f<sub>T</sub>, leading to larger μ<sub>eff</sub> from the elimination of shallow trench isolation (STI) stress.</p>

Monolithic optical link in silicon-on-insulator CMOS technology.

This work presents a monolithic laterally-coupled wide-spectrum (350 nm < λ < 1270 nm) optical link in a silicon-on-insulator CMOS technology. The link consists of a silicon (Si) light-emitting diode (LED) as the optical source and a Si photodiode (PD) as the detector; both realized by vertical abrupt n+p junctions, separated by a shallow trench isolation composed of silicon dioxide. Medium trench isolation around the devices along with the buried oxide layer provides galvanic isolation. Optical coupling in both avalanche-mode and forward-mode operation of the LED are analyzed for various designs and bias conditions. From both DC and pulsed transient measurements, it is further shown that heating in the avalanche-mode LED leads to a slow thermal coupling to the PD with time constants in the ms range. An integrated heat sink in the same technology leads to a ∼ 6 times reduction in the change in PD junction temperature per unit electrical power dissipated in the avalanche-mode LED. The analysis paves way for wide-spectrum optical links integrated in smart power technologies.

Model Quality Evaluation in Semiconductor Manufacturing Process With EWMA Run-to-Run Control

Exponentially weighted moving average run-to-run (EWMA-RtR) controller is frequently adopted in semiconductor manufacturing process. As a model-based control method, the performance of EWMA-RtR controller greatly depends on the process model quality, hence the process model-plant mismatch is an important factor influencing the control performance. In this paper, a model quality evaluation method for semiconductor manufacturing process with EWMA-RtR control is proposed without introducing any external excitation. The white noise sequences are first obtained from the routine closed-loop data by an orthogonal projection method and a disturbance model is estimated from the output error by recursive extended least square method. A model quality variable is then defined and calculated using the disturbance model and the output error. The model evaluation index is proposed using the ratio between the variance of the estimated white noise and that of the model quality variable. The effectiveness of the proposed method is demonstrated by a simulated chemical mechanical polishing process and a shallow trench isolation etch process based on industrial data.

The Challenge of Measuring Strain in FDSOI Device Structures – HRXRD as a Potential Method of Resolution

The strain state of Si1‐xGex/SiO2 dummy structures on FDSOI wafers is non‐destructively characterized by HRXRD reciprocal space mapping. A transition from biaxial to uniaxial strain is detected on narrow condensed Si1‐xGex lines with shallow trench isolation (STI), revealing an increasing in‐plane elastic strain relaxation perpendicular to the trenches with decreasing line width, but no strain relaxation parallel to the trenches. The degree of crystallinity of Si1‐xGex lines degrades with increasing annealing temperature and time. An additional elastic strain reduction appears in the direction parallel to the STI trenches after deposition of source‐drain Si1‐yGey islands between dummy gates. The separation of the Si1‐xGex peaks from Si1‐yGey remains unresolved if x and y are close to each other.

Total Ionizing Dose Response of Multiple-Gate Nanowire Field Effect Transistors

This paper investigates the total ionizing dose (TID) response of nanoscaled field-effect transistors (FET) made of silicon multiple-gate nanowire (NW). The NWFET architecture relies on its remarkable electrostatic properties to push “silicon”-based technologies much deeper into device scaling than present FinFETs. However, as commonly observed when a new device or technology concept is proposed, such as shallow trench isolation and silicon-on-insulator or FinFET, TID effects reveal unexpected behaviors that can permanently modify pristine device electrical characteristics. This is why this paper discusses the impact of several parameters including the NWFET design and the transistor’s type to get thorough insights into the NWFET TID behavior.

Post Cleaning for FEOL CMP with Silica and Ceria Slurries

Post cleaning experiments for front end of the line (FEOL) CMP with silica and ceria slurries are carried out on commercial polishers with 300 mm oxide, nitride, and integrated shallow trench isolation (STI) wafers. Considering the charge attraction or repulsion between particles and wafer surface, both acidic and basic clean chemicals are applied at different stages in the post CMP process sequence. Diluted hydrogen peroxide in a non-contact megasonic cleaner is used to remove ceria abrasive particles and polish residues with high efficiency. On-platen buff clean with or without pad conditioning can make an impact on the post CMP cleaning performance. Post CMP cleaning splits are executed in order to evaluate the effectiveness of each of the process steps and their roles in the overall cleaning performance.

Parametrization of the radiation induced leakage current increase of NMOS transistors

The increase of the leakage current of NMOS transistors during exposure to ionizing radiation is known and well studied. Radiation hardness by design techniques have been developed to mitigate this effect and have been successfully used. More recent developments in smaller feature size technologies do not make use of these techniques due to their drawbacks in terms of logic density and requirement of dedicated libraries. During operation the resulting increase of the supply current is a serious challenge and needs to be considered during the system design. A simple parametrization of the leakage current of NMOS transistors as a function of total ionizing dose is presented. The parametrization uses a transistor transfer characteristics of the parasitic transistor along the shallow trench isolation to describe the leakage current of the nominal transistor. Together with a parametrization of the number of positive charges trapped in the silicon dioxide and number of activated interface traps in the silicon to silicon dioxide interface the leakage current results as a function of the exposure time to ionizing radiation. This function is fitted to data of the leakage current of single transistors as well as to data of the supply current of full ASICs.

Effects of Channel Implant Variation on Radiation-Induced Edge Leakage Currents in n-Channel MOSFETs

The effects of radiation-induced defects and statistical variation in the dose and energy of MOSFET channel implants in a modern bulk CMOS technology are modeled using a process simulator in combination with analytical computations. The model integrates doping profiles obtained from process simulations and experimentally determined defect potentials into implicit surface potential equations. Solutions to these equations are used to model radiation-induced edge leakage currents in 90-nm bulk CMOS n-channel MOSFETs. The results indicate that slight variations in the channel implant parameters can have a significant impact on the doping profile along the shallow trench isolation sidewall and thus the radiation-induced edge leakage currents.

RESURF Model and Electrical Characteristics of Finger-Type STI Drain Extended MOS Transistors

Finger-type shallow trench isolation (finger STI) drain extended MOS transistors are fabricated and its electrical characteristics is studied. Polyplate on a finger STI served as a reduced surface field is adopted to enhance breakdown voltage (BV) by reducing the effective doping concentration of the drain extension (DE) finger. The conformal mapping method, which relates the reduction of the doping concentration to the width ( $z_{o}$ ) of the DE finger, the gap ( $z_{d}$ ) between the polyplate and the DE finger, and the STI depth $y_{s}$ , is used to estimate the reduction of the doping concentration theoretically. Based on this reduced doping concentration, a BV model is derived. The predictions of this model agree very well with the experimental data.

Robust reliability and electrical performances by the bulk-contact modulation in 60-V p-channel LDMOS power components

ABSTRACTTo increase reliability and electrical performance, shallow-trench isolation (STI) (or called field-oxide (FOX)) structures were inserted in the bulk-contact region of 60-V high-voltage p-channel lateral-diffused MOSFET (pLDMOS) devices in this study. As the FOX ratio increased with the addition of FOX segments, the value of the secondary breakdown current (It2) was enhanced. Therefore, the anti-electrostatic discharge ability of a pLDMOS device can be efficiently improved using this novel method. In addition, when the weighting ratio of FOX structures increased, variation values in the trigger voltage (Vt1) and holding voltage (Vh) of the corresponding samples remained within the range of approximately 1–4 V. The Ron value decreased because of more uniform conduction. The experimental data for the FOX structures added to the bulk revealed that the It2 value was improved by approximately 13.98%, Vh values were greater than 60 V (which is favorable for latch-up immunity), and the Ron value was decreased by approximately 12.62% compared with a reference device under test (without FOX segments in the bulk-contact region).

Super junction LDMOS with step field oxide layer

A novel step-oxide super junction-lateral double-diffused metal-oxide-semiconductor field-effect transistor (SOSJ-LDMOS) structure is proposed and optimised which allows the high breakdown voltage (BV) and low-specific on-resistance ( R on,sp ). The proposed structure overcomes the effect of thick field oxide formed by shallow trench isolation process in conventional buffer layer SJ-LDMOS ( N -buffered SJ-LDMOS), effectively enhancing the performance of the SJ-LDMOS. Thanks to the SO layer, a new electric field peak has been introduced in the surface electric field distribution, which makes the lateral surface electric field uniform in the off-state. Moreover, due to the thinner oxide layer, in the on-state the majority of electron current is accumulated near the top surface under the field plate and the thinner oxide layer also provides a wider current flowing path. In the virtue of integrated systems engineering (ISE) simulation, not only has the BV of SOSJ-LDMOS been increased, but also the R on,sp has been reduced simultaneously compared with the N -buffered SJ-LDMOS in the same drift length. In addition, when SOSJ-LDMOS and N -buffered LDMOS are at the same BV, the R on,sp of SOSJ-LDMOS is decreased by 26.3-38.9%, compared with the N -buffer SJ-LDMOS.

Comprehensive effects of strained Ge1−xSnx and device layout arrangement on a nano-scale Ge-based PMOSFET with a short channel

Layout patterns, including salient gate width and dummy active diffusion region (dummy OD), significantly influence the carrier mobility gain of nano scale devices. Germanium (Ge)-based devices with Ge–tin (GeSn) alloy embedded in the source/drain (S/D) regions have been regarded a promising candidate for higher channel mobility. Second-order piezoresistance coefficients were used to estimate the carrier mobility gain within the desired Ge-based device channel. A 20nm Ge-based p-type metal oxide semiconductor field effect transistor with 100nm gate width and 100nm dummy OD width was selected to explore the layout effect of the short channel device. The device consisted of S/D region Ge1−xSnx alloy, compressive-stressed contact etch stop layer, and deposited shallow trench isolation with different process-induced stress magnitudes. Maximum carrier mobility gain of 93.65% was obtained when a 10nm narrow distance between OD and dummy OD was achieved.

Split CV mobility at low temperature operation of Ge pFinFETs fabricated with STI first and last processes

The effective hole mobility of long strained Ge pFinFETs, fabricated with shallow trench isolation (STI) first and last approaches, is systematically evaluated from room temperature down to 77 K, from planar-like (100 nm) to narrow (20 nm) devices. The goal is to identify the dominant scattering mechanism. Here, the split capacitance-voltage (CV) technique has been applied, based on combined current–voltage (I–V) and CV measurements. It is shown that even at 77 K, the phonon scattering mechanism dominates the STI last process, while the Coulomb scattering strongly affects the STI first approach. On the other hand, the latter shows slightly higher hole mobility compared to the STI last counterpart.