Abstract
The increase of the leakage current of NMOS transistors during exposure to ionizing radiation is known and well studied. Radiation hardness by design techniques have been developed to mitigate this effect and have been successfully used. More recent developments in smaller feature size technologies do not make use of these techniques due to their drawbacks in terms of logic density and requirement of dedicated libraries. During operation the resulting increase of the supply current is a serious challenge and needs to be considered during the system design. A simple parametrization of the leakage current of NMOS transistors as a function of total ionizing dose is presented. The parametrization uses a transistor transfer characteristics of the parasitic transistor along the shallow trench isolation to describe the leakage current of the nominal transistor. Together with a parametrization of the number of positive charges trapped in the silicon dioxide and number of activated interface traps in the silicon to silicon dioxide interface the leakage current results as a function of the exposure time to ionizing radiation. This function is fitted to data of the leakage current of single transistors as well as to data of the supply current of full ASICs.
Highlights
The radiation induced leakage current of NMOS transistors and the threshold voltage shift are well known and intensively studied challenges for the design of radiation hard application specific integrated circuits (ASIC)
With the transition to the 0.13 μm technology node, the amplitude of the leakage current increase decreases by three orders of magnitude, with the result that the Hardness by design (HBD) techniques are needed in sensitive nodes of the design only for radiation hard designs [4]
As demonstrated in this paper, this parametrization can be used as well to model the supply current shift with total ionizing dose (TID) on full ASICs and to predict the current to be expected during operation of the ASICs as a function of the temperature and the dose rate, once the parameters of the parametrization are measured
Summary
The radiation induced leakage current of NMOS transistors and the threshold voltage shift are well known and intensively studied challenges for the design of radiation hard application specific integrated circuits (ASIC). The HBD techniques consist mainly of the use of enclosed gate transistors to mitigate the source to drain leakage current along the shallow trench isolation (STI) and guard ring structures surrounding the transistors to avoid leakage current between neighboring structures. The use of this technique requires an increased area as well as custom libraries. With the transition to the 0.13 μm technology node, the amplitude of the leakage current increase decreases by three orders of magnitude, with the result that the HBD techniques are needed in sensitive nodes of the design only for radiation hard designs [4]. As demonstrated in this paper, this parametrization can be used as well to model the supply current shift with TID on full ASICs and to predict the current to be expected during operation of the ASICs as a function of the temperature and the dose rate, once the parameters of the parametrization are measured
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