Abstract

Silicon-on-insulator (SOI) technologies have been developed for radiation-hardened applications for many years and are rapidly becoming a main-stream commercial technology. The total dose response of SOI devices is more complex than for bulk-silicon devices due to the buried oxide. Radiation-induced trapped charge in the buried oxide can increase the leakage current of partially-depleted transistors and decrease the threshold voltage and increase the leakage current of fully-depleted transistors. We review process and design techniques that have been developed to reduce the net amount of radiation-induced positive charge trapped in the buried oxide or to mitigate the effects of trapped charge in the buried oxide, respectively. We also compare the total dose response of devices operated in single-gate (SG) and double-gate (DG) mode as a function of silicon film thickness. DG-MOSFETs are systematically less sensitive to radiation-induced trapped charge and interface trap.

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