Analysis and optimization of RC delay in vertical nanoplate FET

Abstract

In this paper, we have analyzed short channel effects (SCEs) and RC delay with Vertical nanoplate FET (VNFET) using 3-D Technology computer-aided design (TCAD) simulation. The device is based on International Technology Road-map for Semiconductor (ITRS) 2013 recommendations, and it has initially gate length (LG) of 12.2nm, channel thickness (Tch) of 4nm, and spacer length (LSD) of 6nm. To obtain improved performance by reducing RC delay, each dimension is adjusted (LG=12.2nm, Tch=6nm, LSD=11.9nm). It has each characteristic in this dimension (Ion/Ioff=1.64×105, Subthreshold swing (S.S.)=73mV/dec, Drain-induced barrier lowering (DIBL)=60mV/V, and RC delay=0.214ps). Furthermore, with long shallow trench isolation (STI) length and thick insulator thickness (Ti), we can reduce RC delay from 0.214ps to 0.163ps. It is about a 23.8% reduction. Without decreasing drain current, there is a reduction of RC delay as reducing outer fringing capacitance (Cof). Finally, when source/drain spacer length is set to be different, we have verified RC delay to be optimum.