Set Of Test Patterns Research Articles

On the use of counters for reproducing deterministic test sets

We propose a very simple and fast CAD tool to check whether a binary counter can reproduce a predetermined set of test patterns in a reasonable time. Given a test matrix T, the tool uses column merging, complementation, and permutation so that the distance between the starting and the finishing vector of the corresponding counter is minimized. The hardware overhead of the proposed approach is by far lower than that of any other existing approach. Although it is computationally difficult (NP-hard) to obtain the absolute minimum distance, we present an algorithm which in the absence of don't cares in the test matrix, finds an appropriate column merging, complementation, and permutation that guarantees the distance is never more than twice as large as the best possible. In the presence of don't cares, the latter algorithm forms the basis of a powerful heuristic. Experiments on various test sets on benchmark circuits show that the exact number of clock cycles needed for a binary counter to reproduce all the patterns for the hard-to-detect faults compares favorably with the expected number yielded by existing Weighted Random LFSR-based approaches which have significantly higher hardware overhead.

Defect level evaluation in an IC design environment

The purpose of this paper is to present a methodology for the evaluation of the Defect Level in an IC design environment. The methodology is based on the extension of Williams-Brown formula to nonequiprobable faults, which are collected from the IC layout, using the information on a typical IC process line defect statistics. The concept of weighted fault coverage is introduced, and the Defect Level (DL) evaluated for the Poisson and the negative binomial yield models. It is shown that DL depends on the critical areas associated with undetected faults, and their correspondent defect densities. Simulation results are presented, which highlight that the classic single Line Stuck-At (LSA) fault coverage is a unreliable metric of test quality. Moreover, results show that the efficiency of a given set of test patterns strongly depends on the physical design and defect statistics.

Generating test patterns for VLSI circuits usinga geneticalgorithm

The authors present the development of a technique that uses genetic algorithms, for the generation of test patterns that detect single stuck-at faults in combinational VLSI circuits. As the genetic algorithm evolves, an efficient set of test patterns are produced, by searching the solution space for patterns that detect the highest number of remaining faults in the fault list.

Diagnosis of multiple stuck-at type faults and bridge faults in combinational circuits with redundant wires

Behavior of a combinational circuit under the presence of a multiple stuck-at type fault and/or bridge faults, is analyzed. The circuit is assumed to be made up of AND, NAND, OR, NOR, and NOT gates, for simplicity of presentation of this paper. There are no other restrictions on the circuit structure. An algorithm is developed to enumerate different types of paths in the circuit, to determine a set of the primary input combinations to sensitize each path according to a well defined path sensitizing criterion, and finally to obtain a set of test patterns with a diagnostic resolution to locate all detectable components of the multiple fault and/or the bridge-faults present in the circuit. The last part of the algorithm builds a fault dictionary for the circuit under test. A theory is presented to prove the completeness of the diagnostic resolution of the obtained test-set. The theory is extended to show how a larger test-set obtained from the same algorithm can diagnose all multiple faults and/or bridge-faults in the circuits that contain undetectable faults and redundant wires.

A new technique for measuring coupling coefficients and 3-D capacitance characterization of floating-gate devices

The characteristics of the capacitance in floating-gate devices are comprehensively investigated. The capacitive coupling coefficient (/spl alpha//sub c/) between the control and floating gates is measured simultaneously, by a new technique, with the shift in threshold voltage during the programming. The present results are compared with those found from other methods and the dependence of /spl alpha//sub c/ on applied voltages is examined. It is also shown that the /spl alpha//sub c/-data from a set of test patterns with varying floating-gate widths leads to the 3-D characterization of small geometry floating gate devices down to subfemto Farads. These measured characteristics are discussed in correlation with the effects of both the short channel length and of the narrow gate width.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Testability and test generation for majority voting fault-tolerant circuits

The testability of majority voting based fault-tolerant circuits is investigated and sufficient conditions for constructing circuits that are testable for all single and multiple stuck-at faults are established. The testability conditions apply to both combinational and sequential logic circuits and result in testable majority voting based fault-tolerant circuits without additional testability circuitry. Alternatively, the testability conditions facilitate the application of structured design for testability and Built-In Self-Test techniques to fault-tolerant circuits in a systematic manner. The complexity of the fault-tolerant circuit, when compared to the original circuit can significantly increase test pattern generation time when using traditional automatic test pattern generation software. Therefore, two test pattern generation algorithms are developed for detecting all single and multiple stuck-at faults in majority voting based circuits designed to satisfy the testability conditions. The algorithms are based on hierarchical test pattern generation using test patterns for the original, non-fault-tolerant circuit and structural knowledge of the majority voting based design. Efficiency is demonstrated in terms of test pattern generation time and cardinality of the resulting set of test patterns when compared to traditional automatic test pattern generation software.

Confidence intervals for expected coverage from a beta testability model

The testability distribution of a VLSI circuit can be used to predict the fault coverage of a set of test patterns by restricting the standard test pattern generation process to a sample of faults. When testability of a VLSI circuit is modeled as a beta distribution, the random detection counts obtained have a beta-binomial distribution. This paper includes: a) three confidence intervals for the parameters of the beta-binomial distribution; b) a determination of the proper sample size needed such that the theoretical confidence intervals agree with the actual ones; and c) a determination of the effect of the number of generated tests on confidence interval widths. Restricting the test generation process to a sample of faults results in major savings in the overall costs of test generation. Experimental results are given on three of the large combinational benchmark circuits (presented at the 1985 International Symposium on Circuits and Systems).

Combined probabilistic testability calculation and compact test generation for PLAs

PLAs (programmable logic arrays) may be tested internally by self-test, or externally by applying test patterns. Fault coverage by nonexhaustive self-test is assured by computing a lower bound for estimated fault coverage vs. test pattern number. First, a lower bound for probabilistic detectability per fault is computed by a method based on Shannon's expansion theorem. In the process of finding a lower bound detectability for a particular fault, a test pattern for the fault is generated automatically, at no extra cost. These patterns often contain several don't cares. Traditional test pattern compaction is then applied to the test pattern set. In addition, a novel test pattern compaction method is introduced, suitable for embedded circuitry. The method may be used in conjunction with a serial scan architecture, whereby each test pattern is shifted one position before being applied to the circuit under test. The compaction scheme was applied to a benchmark set of 53 PLAs. An average reduction of 70% in the number of test bits and clock cycles was achieved.1

Testing interconnections to static RAMs

A method for testing the interconnections of ordinary static RAMs with a processor that has a boundary-scan register and an IEEE 1149.1 test-access port is described. The method uses an enhanced boundary-scan-register design that manipulates the test-access-port controller states to meet the static RAM's timing constraints. The implementation is more economical than a boundary-scan register that strictly conforms to IEEE 1149.1. Test operation is more efficient, requiring a third of the number of scan operations. A test-pattern set and a method for detecting and diagnosing the interconnection faults on RAMs are also described. The test-pattern set can be enhanced as necessary to increase coverage and diagnosing ability and to handle any RAM configuration. The implementation of the proposed boundary-scan register is independent of the test algorithm used. It is believed that the methodology is extendable to RAMs that use an access protocol different from the one described, for example dynamic RAMs and synchronous RAMs.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Assessing the diagnostic power of test pattern sets

The increasing power of the available fault simulators makes it possible to satisfy new requirements such as statistics and other data about both the testability and the diagnosability of circuits. Commercial fault simulators are often unable to provide this kind of information and, even when they provide some diagnostic facilities, they are highly inefficient in implementing them. This paper introduces a general framework to analyze the problem and presents an ad hoc strategy based on efficient techniques for both simulation and fault dropping. A prototype simulator, able to produce full diagnostic information with acceptable CPU time and memory requirements, is described.

Verification Method of Software for Microprocessor-Based Protection System of Nuclear Power Plants

This paper proposes a new concept for efficient verification of software for the protection systems of nuclear power plants. In this idea, all possible input combinations are applied to each module comprising the software and the module responses are compared with their correct responses which are provided beforehand. To realize the concept, algorithms have been developed for observing module responses through an external tester and for generating a quasi minimal test pattern set capable of testing all modules. This approach remarkably reduces the number of required test input combinations in comparison with that of the combinations without observation of module outputs. In addition, most software errors are expected to be uncovered more efficiently with less effort and time.

Detection of stuck-at and bridging faults in reed—muller canonical (RMC) networks

Boolean function realisations by Reed—Muller networks have many desirable properties in terms of testability [11]. In the paper it is shown that there exists a single set of test patterns which would detect all single stuck-at and all single bridging (short-circuit) faults in Reed-Muller networks, and the number of test patterns is shown to be at most 3n + 5, where n is the number of input variables in the function. In the case of networks with k outputs, where k ≤ 2n, the number of test patterns required to detect all single stuck-at and all single detectable bridging faults (both AND and OR) is also shown to be 3n + 5.

Verification method of software for microprocessor-based protection system of nuclear power plants.

This paper proposes a new concept for efficient verification of software for the protection systems of nuclear power plants. In this idea, all possible input combinations are applied to each module comprising the software and the module responses are compared with their correct responses which are provided beforehand. To realize the concept, algorithms have been developed for observing module responses through an external tester and for generating a quasi minimal test pattern set capable of testing all modules. This approach remarkably reduces the number of required test input combinations in comparison with that of the combinations without observation of module outputs. In addition, most software errors are expected to be uncovered more efficiently with less effort and time.

Noise Problems in Testing VLSI Hardware

Noise resulting from the switching of high-current, off-product drivers in VLSI circuits cause substantial problems during manufacturing test and may lead to zero yield. These problems, seldom addressed during product design, can be mitigated or eliminated either during the design phase or at mauufacturing test. In this article, we present some of our experiences with noise during manufacturing test, and discuss several solutions to the problem. These remedies include such manufacturing test options as relaxing the test specification, or "guardbanding" which requires both substantial study of the impact on quality and continual tracking of the problem level; modifying the test program to eliminate the need for a guardband; or having the logic designer create a new set of functional test patterns specifically designed to avoid simultaneously switching drivers. We also examine alternative design methods for use during both product and tester design.

Design of Totally Self-Checking Comparators with an Arbitrary Number of Inputs

Two new general designs for totally self-checking (TSC) comparators with an arbitrary number of input vectors are presented. The multipattern comparator combines modified TSC 2-input comparators and a TSC two-rail checker that requires only four patterns for self-testing. The counter-driven comparator adds circuitry to generate an exhaustive set of test patterns. The designs are compared on the basis of input limitations, circuit complexity, and gate delays. It is shown that TSC comparators cannot exist under two sets of conditions associated with 1-bit input vectors and two-level circuit realizations.

Iterative Exhaustive Pattern Generation for Logic Testing

Exhaustive pattern logic testing schemes provide all possible input patterns with respect to an output in the set of test patterns. This paper is concerned with the problem that arises when this is to be done simultaneously with respect to a number of outputs, using a single test set. More specifically, in this paper we describe an iterative procedure for generating a test set consisting of n-dimensional vectors which exhaustively covers all k-subspaces simultaneously, i.e., the projections of n-dimensional vectors in the test set onto any input subset of a specified size k contain all possible patterns of k-tuples. For any given k, we first find an appropriate N (N>k) and generate an efficient N-dimensional test set for exhaustive coverage of all k-subspaces. We next develop a constructive procedure to expand the corresponding test matrix (formed by taking test vectors as its rows) such that a test set of N <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> -dimensional vectors exhaustively covering the same k-subspaces is obtained. This procedure may be repeated to cover arbitrarily large n (equation after i iterations), while keeping the same k. It is shown that the size of the test set obtained this way grows in size which becomes proportional to (log n) raised to the power of [log (q+1)], where q is a function of k only, and is approximated (bounded closely below) by k <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /4 in binary cases. This approach applies to nonbinary cases as well except that the value of q in an r-ary case is approximated by a number lying between k <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /4 and k <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /2.

The Self-Testing of a Solid State Safety System

An automatic, on-line self-test system is employed in the General Electric BWR/6 solid state Nuclear System Protection System (NSPS) control room cabinets to rapidly detect hardware failures and facilitate repair. Each of the four NSPS cabinets in the control room contains a microprocessor based selftest controller in whose memory are stored sets of input stimulii test patterns and expected output results. For each set of input patterns the expected and actual outputs are compared and discrepancies annunciated to the plant's operators. These sets of test patterns comprehensively test all essential circuits and wiring within and between the NSPS cabinets such that the self-test system is able to determine the exact location of all failures in safety related hardware. The cabinets were designed to ensure that operation of and failures in the selftest system do not influence the correctness of the safety system's outputs.

Control system design and alignment methods for electron lithography

The electron-beam exposure system (EBES) was designed to economically expose integrated circuit masks on a production basis and to directly pattern semiconductor substrates for special applications where a limited number of devices are required. The machine was designed to assure absolute pattern accuracy over the entire substrate so that masks made by EBES will be interchangable with those made by our optical mask shop or those made by later electron-beam pattern generators. This has been achieved by a combination of control system design and by automated periodic system alignment. The control system design utilizes a laser interferometer to determine precise table position and a feedback system that continuously corrects the writing-beam location for errors in table location. This combination, coupled with a small-angle electron-beam deflection system using an ultrastable sawtooth-scan generator to achieve repeatable beam positioning over a small writing area, allows exposure rates of 107 addresses per second with submicron absolute accuracies over a 10×10-cm area. A series of automated measurements have been implemented in order to maintain this accuracy for extended periods. Every five minutes beam-positioning errors resulting from external magnetic fields, temperature variations, and amplifier drifts are measured by using the electron column as a scanning electron microscope to locate a registration mark permanently affixed to the table. Several times a day, the deflection system is automatically adjusted under computer control to assure that the electron-beam deflection axes agree precisely with the interferometer-controlled table motion in both magnitude and direction. Periodically, a set of special test patterns are written by EBES and then, using EBES as a computer-controlled coordinate measuring machine, these patterns are measured and analyzed to provide an accurate assessment of the machine’s true writing performance. This alerts the mask shop to potential problems and allows service personnel to make the necessary corrections before the final product is materially affected.

An Algorithm for Selecting an Optimum Set of Diagnostic Tests

In the design of combinational diagnostic testing procedure for a large digital system, some redundant tests are expected. This paper describes an algorithm for selecting a good (locally optimized) set of diagnostic tests which contains no redundancy. The algorithm will in general tend to give a ``fairly good'' set of test patterns, but is not guaranteed to be absolutely minimal. An overall optimization scheme is desirable but seems impractical [1]. The procedure described can be used either to yield a set of diagnostics which loses no resolution from the full set, or to yield a smaller set with some loss in resolution.