Combined probabilistic testability calculation and compact test generation for PLAs

Abstract

PLAs (programmable logic arrays) may be tested internally by self-test, or externally by applying test patterns. Fault coverage by nonexhaustive self-test is assured by computing a lower bound for estimated fault coverage vs. test pattern number. First, a lower bound for probabilistic detectability per fault is computed by a method based on Shannon's expansion theorem. In the process of finding a lower bound detectability for a particular fault, a test pattern for the fault is generated automatically, at no extra cost. These patterns often contain several don't cares. Traditional test pattern compaction is then applied to the test pattern set. In addition, a novel test pattern compaction method is introduced, suitable for embedded circuitry. The method may be used in conjunction with a serial scan architecture, whereby each test pattern is shifted one position before being applied to the circuit under test. The compaction scheme was applied to a benchmark set of 53 PLAs. An average reduction of 70% in the number of test bits and clock cycles was achieved.1