Abstract
The authors present a built-in self-test (BIST) programmable logic array (PLA) design in CMOS technology that provides a high percentage of coverage for multiple stuck-at, crosspoint, and bridging faults and, furthermore detects all simple stuck-open faults in the AND and OR planes and all multiple stuck-open faults in the AND plane. As the test patterns used are the same for all PLAs, a universal test for PLAs is defined. The hardware overhead complexity for this scheme resembles that of previous proposals, although the number of different test patterns used has been reduced. >
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
