Abstract
Presents a complete fault-tolerant programmable logic array (PLA) design that includes both fault diagnosability and repairability. The proposed PLA design is capable of detecting, locating, and repairing single and multiple stuck-at, bridging, and crosspoint faults. The results of this study show that the total augmented area overhead for both repair and fault diagnosis is nearly 15 to 25 percent over the original PLA, but the chip yield can be improved significantly. >
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